Ping Gui

The GBT Project

The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planned for the SLHC, the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs address this issue implementing a radiation-hard bi-directional 4.8 Gb/s optical fibre link between the counting room and the experiments. The paper describes in detail the GBT-SERDES architecture and presents an overview of the various components that constitute the GBT chipset.

The GBTIA, a 5 Gbit/s Radiation-Hard Optical Receiver for the SLHC Upgrades

The GigaBit Transceiver (GBT) is a high-speed optical transmission system currently under development for HEP applications. This system will implement bi-directional optical links to be used in the radiation environment of the Super LHC. The GigaBit Transimpedance Amplifier (GBTIA) is the front-end optical receiver of the GBT chip set. This paper presents the GBTIA, a 5 Gbit/s, fully differential, and highly sensitive optical receiver designed and implemented in a commercial 0.13 µm CMOS process. When connected to a PIN-diode, the GBTIA displays a sensitivity better than 19 dBm for a BER of 10 12 . The differential output across an external 50  load remains constant at 400 mVpp even for signals near the sensitivity limit. The chip achieves an overall transimpedance gain of 20 k with a measured bandwidth of 4 GHz. The total power consumption of the chip is less than 120 mW and the chip die size is 0.75 mm x 1.25 mm. Irradiation testing of the chip shows no performance degradation after a dose rate of 200 Mrad.

Lifetime Studies of 130 nm nMOS Transistors Intended for Long-Duration, Cryogenic High-Energy Physics Experiments

Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130 nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300 K and at 77 K can be projected to more than 20 years at the nominal voltage (1.5 V) for this technology.

Single-Event Upsets in Photoreceivers for Multi-Gb/s SLHC Data Transmission

A 63 MeV proton beam was used to perform a single event upset (SEU) test on a candidate component for a future high luminosity large hadron collider (HL-LHC) high speed optical. An in-lab error injector was used to show that 1-0 bit errors are caused by the amplifiers response to the large signal caused by a single event transient (SET) in the photodiode.

Low-phase-noise 54GHz quadrature VCO and 76GHz/90GHz VCOs in 65nm CMOS process

This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave Quadrature VCO (QVCO) and VCOs. A transformer coupling with extra phase shift is proposed in QVCO to decouple the tradeoff between phase noise (PN) and phase error and improve the PN performance. This technique is demonstrated in a mmWave QVCO with a measured PN of -119.2 dBc/Hz at 10 MHz offset of a 56.2 GHz carrier and a tuning range of 9.1% (FOMT of -179 dBc/Hz). To our best knowledge, this QVCO has the lowest PN at 10 MHz offset among all the QVCOs around 50-60 GHz frequency range. In addition, an inductive divider feedback technique is proposed in VCO design to improve the transconductance linearity, resulting in larger signal swing and lower PN compared to the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76 GHz VCO and a 90 GHz VCO, both fabricated in a 65 nm CMOS process, with an FOMT of 173.6 dBc/Hz and 173.1 dBc/Hz, respectively.

Gigabit switch using free-space and parallel optical data links for a PCI-based workstation cluster

Communication requirements in high-performance, parallel computing systems continue to increase as the processing nodes within these systems gain processing capability. To support these growing communication requirements, system architecture changes are needed. The use of switched networks rather than bus-based systems and the incorporation of optical interconnects are among proposed solutions to increase overall system performance. Under the VIVACE program, we combine both of these approaches to demonstrate a switched network of 12-Gb/s raw data bandwidth using a 4 Tbit/s bisection bandwidth free-space optically interconnected (FSOI) switch. The optical-interconnect based VIVACE network is accessed by compute nodes through the use of an electrical network interface card (NIC) which provides custom VIVACE protocol conversion in addition to the necessary electrical and optical conversions.

An NMOS low dropout voltage regulator with switched floating capacitor gate overdrive

This paper presents a 1.5 V 50 mA low dropout voltage (LDO) regulator using an NMOS transistor as the output pass element. Continuous time operation of the LDO is achieved using a new switched floating capacitor scheme that raises the gate voltage of the pass element. The regulator has a 0.1 V dropout at a 50 mA load and is stable for a wide load current range with loading capacitances up to 100 pF. The output variation when a full load step is applied is 35 mV and the recovery time is below 0.6 µs. It is designed in a 0.13 µm CMOS process with an area of 0.018 mm2 and does not require any external component.

A 2-Gb/s 0.5-/spl mu/m CMOS parallel optical transceiver with fast power-on capability

This paper describes an optical transceiver designed for power-efficient connections within high-speed digital systems, specifically for board- and backplane-level interconnections. A 2-Gb/s, four-channel, dc-coupled differential optical transceiver was fabricated in a 0.5-/spl mu/m complementary metal-oxide-semiconductor (CMOS) silicon-on-sapphire (SoS) process and incorporates fast individual-channel power-down and power-on functions. A dynamic sleep transistor technique is used to turn off transceiver circuits and optical devices during power-down. Differential signaling (using two optical channels per signal) enables self-thresholding and allows the transceiver to quickly return from power-down to normal operation. A free-space optical link system was built to evaluate transceiver performance. Experimental results show power-down and power-on transition times to be within a few nanoseconds. Crosstalk measurements show that these transitions do not significantly impact signal integrity of adjacent active channels.

Degradations of Threshold Voltage, Mobility, and Drain Current and the Dependence on Transistor Geometry For Stressing at 77 K and 300 K

Based on test results and a procedure that can isolate threshold voltage degradation and mobility degradation from drain current degradation, we found that the log-log curves of mobility degradation show saturation with a change of slope from about 0.4 to smaller values at room temperature. Although both the mobility and threshold voltage degradations are more severe at 77 K than at 300 K for the same stress time, the temperature effect on the mobility degradation is larger than that on the threshold voltage degradation. In addition, the degradations of transistors with three different widths are compared after the stress tests at room and cryogenic temperatures, leading to the observation of degradation dependence on the transistor width. It is observed that the width dependence is more evident at 300 K, and the temperature plays a more significant role on the degradation for larger width transistors.

An Integrated High-Voltage Low-Distortion Current-Feedback Linear Power Amplifier for Ultrasound Transmitters Using Digital Predistortion and Dynamic Current Biasing Techniques

A novel integrated high-voltage linear power amplifier for medical ultrasonic transmitter applications is presented in this brief. The amplifier employs a current-feedback technique with two cascading push-pull class-AB buffers. It overcomes the gain-bandwidth product limitation of a conventional voltage-feedback amplifier, capable of generating high output signal swing with a wide closed-loop bandwidth. In addition, a dynamic current biasing topology is integrated on-chip using a voltage-controlled current source and a 7-bit digital-to-analog converter (DAC). To further improve the signal linearity of the amplifier output, a digital predistortion (DPD) technique is applied by using a DAC, an analog-to-digital converter, and a digital field-programmable gate array. The presented amplifier was fabricated using a 1-μm 200-V CMOS process. The measurement results show that this integrated linear power amplifier is capable of driving a load of a 100-Ω resistor in parallel with a 300-pF capacitor while achieving a signal swing up to 180 Vpp with a second-order harmonic distortion as low as -50 dB. Measurement results also show that the amplifier achieves a maximum slew rate of 4 V/ns and a power efficiency of 30%. As a result, this power amplifier is expected to greatly improve medical ultrasound image quality.