Marko S. Andjelkovic

Using RADFET for the real-time measurement of gamma radiation dose rate

RADFETs (RADiation sensitive Field Effect Transistors) are integrating ionizing radiation dosimeters operating on the principle of conversion of radiation-induced threshold voltage shift into absorbed dose. However, one of the major drawbacks of RADFETs is the inability to provide the information on the dose rate in real-time using the conventional absorbed dose measurement technique. The real-time monitoring of dose rate and absorbed dose can be achieved with the current mode dosimeters such as PN and PIN diodes/photodiodes, but these dosimeters have some limitations as absorbed dose meters and hence they are often not a suitable replacement for RADFETs. In that sense, this paper investigates the possibility of using the RADFET as a real-time dose rate meter so that it could be applied for simultaneous online measurement of the dose rate and absorbed dose. A RADFET sample, manufactured by Tyndall National Institute, Cork, Ireland, was tested as a dose rate meter under gamma irradiation from a Co-60 source. The RADFET was configured as a PN junction, such that the drain, gate and source terminals were grounded, while the radiation-induced current was measured at the bulk terminal, whereby the bulk was successively biased with 0 , 10 , 20 and 30 V. In zero-bias mode the radiation-induced current was unstable, but in the biased mode the current response was stable for the investigated dose rates from 0.65 to 32.1 Gy h−1 and up to the total absorbed dose of 25 Gy. The current increased with the dose rate in accordance with the power law, whereas the sensitivity of the current read-out was linear with respect to the applied bias voltage. Comparison with previously analyzed PIN photodiodes has shown that the investigated RADFET is competitive with PIN photodiodes as a gamma radiation dose rate meter and therefore has the potential to be employed for the real-time monitoring of the dose rate and absorbed dose.

The behavior of fixed and switching oxide traps of RADFETs during irradiation up to high absorbed doses.

The behavior of radiation-induced fixed traps (FTs) in gate oxide and radiation-induced switching traps (STs) near and at the gate oxide/substrate interface during irradiation up to high absorbed doses has been considered. The zero-bias voltage regime, the simplest and most popular solution in practice, was chosen. Indeed, it is very difficult to predict the creation of radiation defects in the case of low electric fields, because there is a compromise between the external low electric fields induced by work function differences and the internal electrical fields induced by radiation-induced charged defects in the oxide. It was shown that the density of FTs is higher than the density of STs for lower absorbed doses, though the trend is reversed for doses greater than 700Gy. Although the number of FTs is much higher than the number of STs, many FTs are located in the bulk, far from the oxide/semiconductor interface and their influence on channel carriers is much smaller than the influence of STs that are located closer to the channel. The equation for fitting the threshold voltage components induced by FTs (ΔVft) and by STs (ΔVst) is proposed and very good fittings are obtained. It is shown that five experimental irradiation points are sufficient to draw a good conclusion about the values of the fitting parameters, i.e., the voltage saturation values and the degree of linearity.

An analysis of the operation and SET robustness of a CMOS pulse stretching circuit

The cascaded asymmetrically sized inverters can be employed as pulse stretchers, for the measurement of very short single event transient (SET) pulse widths (< 200 ps). This paper analyzes, through the circuit simulations, the effects of various design and operating parameters on the normal operation and SET robustness of a two-inverter pulse stretcher designed in 250 nm bulk CMOS technology. It was shown that the SET hardness of the pulse stretcher can be enhanced by upsizing all transistors in the pulse stretcher without changing the sizing ratio. The SET hardness can also be improved by upsizing the load, but this approach is less effective than the pulse stretcher upsizing. Both upsizing approaches have a negligible impact on the normal operation of the stretcher, i.e. output pulse width. In addition, the operation and SET robustness of the pulse stretcher can be influenced by the operating temperature and supply voltage variations, and these effects should be considered in the design process. Based on the acquired simulation results, a general approach for the design of a radiation hardened CMOS pulse stretcher has been proposed.

SET response of a SEL protection switch for 130 and 250 nm CMOS technologies

This paper analyzes the single event transient (SET) response of a single event latchup (SEL) protection switch (SPS) designed in the 130 and 250 nm bulk CMOS technologies. The analysis has been conducted through the SPICE simulations, using the standard double exponential current source as the SET model. It has been confirmed that the 130 nm SPS cell is more susceptible to SETs than the 250 nm version, i.e. the 130 nm SPS cell has exhibited significantly lower critical charge. Based on the simulation results, an analytical model for estimating the critical charge in terms of the transistor size, number of load cells, and duration of the SET current pulse, has been derived. Use of the proposed critical charge model simplifies the analysis of the SPS cells susceptibility to SETs for custom designs.

Assessment of the amplitude-duration criterion for SET/SEU robustness evaluation

The relation between amplitude and duration of the current pulse induced by a high energy ionizing particle has been proposed as a criterion for evaluating the SET and SEU robustness of integrated circuits. This criterion has advantage over the widely accepted critical charge concept in the sense that it is less dependent on the current pulse shape. However, to the best of our knowledge, there is no known report on the impact of design and operating parameters on the amplitude-duration criterion. The need for extensive circuit or device simulations to derive the amplitude-duration curves under varying design and operating parameters makes this approach very time-consuming. In that regard, this work proposes a method to establish the amplitude-duration criterion, with a limited number of circuit simulations, as a rational function in terms of the sizing factors of target and load gates and supply voltage. Initial evaluation on a simple circuit composed of two inverters, designed in 130 nm bulk CMOS technology, has shown that the proposed method provides the accuracy comparable to SPICE simulations.

Design of an On-chip System for the SET Pulse Width Measurement

This paper presents a design of an on-chip single event transient (SET) pulse width measurement system. The proposed system has been designed and implemented in IHPs 250 nm bulk CMOS technology and is intended for evaluation of SET effects in standard digital library cells. It is composed of an inverter-based target circuit, a pulse stretcher and a processing unit for counting the SET pulses and measuring the SET pulse width. The realized system is based on the combination of best practices from various existing designs, and it has a fairly simple architecture capable to provide reliable SET characterization. It supports serial interfacing with the external data acquisition unit which transfers the acquired data to the personal computer. The preliminary evaluation through the circuit-level simulations has demonstrated that the proposed design can detect and measure the SET pulse widths from around 100 ps up to 3.5 ns, with the measurement resolution of approximately 100 ps.

Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch

A single event latchup protection switch (SPS) has been developed in the IHP 250 nm bulk CMOS technology. The SPS has been designed as a standard library cell intended for implementation in the radiation-tolerant application specific integrated circuits (ASICs). It provides detection of single event latchup and subsequent shut-down of power supply to critical elements within the chip to restore the normal operation. However, the SPS cell might be also susceptible to single event transients. In that regard, this work presents the simulation-based analysis of the response of SPS cell in the case of single event transients. The dependence of the single event transient response with respect to the injected charge, supply voltage, load and sensing transistors size has been analyzed.