Markus Hiienkari

How low energy is bluetooth low energy? Comparative measurements with ZigBee/802.15.4

Ultra low power communication mechanisms are essential for future Internet of Things deployments. Bluetooth Low Energy (BLE) is one promising candidate for such deployments. We study the energy consumption of BLE by measuring real devices with a power monitor and derive models of the basic energy consumption behavior observed from the measurement results. We investigate also the overhead of Ipv6-based communication over BLE, which is relevant for future IoT scenarios. We contrast our results by performing similar measurements with ZigBee/802.15.4 devices. Our results show that when compared to ZigBee, BLE is indeed very energy efficient in terms of number of bytes transferred per Joule spent. In addition, IPv6 communication energy overhead remains reasonable. We also point out a few specific limitations with current stack implementations and explain that removing those limitations could improve energy utility significantly.

Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery

We introduce an ultra-low-energy system comprised of a prototype 1.55V Li-ion battery, fully integrated switched-capacitor (SC) DC-DC 3:1 converter, and a 32-bit RISC CPU with timing-error prevention (TEP). The DC-DC converter and CPU are manufactured in 28nm UTBB FD-SOI. The DC-DC converter uses the batterys flat discharge curve and low nominal voltage to achieve a peak efficiency of 85%. The CPU operates from 0.3V-0.5V and with energy as low as 4.9pJ/cyc. The battery, DC-DC converter, and CPU system is able to operate with an average energy of 8pJ/cyc over 95% of the batterys discharge curve in the temperature range of -20oC to 70oC.

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.

Rethinking DC-DC converter design constraints for adaptable systems that target the minimum-energy point

This paper explores a new DC-DC converter design constraint for adaptable systems that target the minimum-energy point (MEP). Traditionally, DC-DC converters have regulated to a fixed output voltage over a wide range of input voltages. For energy-constrained systems that target the MEP, regulating them to a fixed voltage is unnecessary since changes in the output voltage near the MEP have little impact on the energy per cycle. This paper applies a new and traditional design constraint to a 3:1 series-parallel switched-capacitor (SC) DC-DC converter in 28 nm CMOS. The new design constraint allows for decreased design time, less area, and less system-level energy per cycle compared to traditional constraints.

Implementing Minimum-Energy-Point Systems With Adaptive Logic

Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. This paper shows that the increased adaptability can be a great advantage in the system design in addition to the well-known mitigated susceptibility to ambient and internal variations. Specifically, the design tolerances of the power management are relaxed to enable even greater system-level energy savings than what can be achieved in the logic alone. In addition, the system is simultaneously able to operate near the minimum error point. Here, the power management is a simplified dc-dc converter and the TED is based on time borrowing. The target application is a single-chip system on chip without external discrete components; thus, switched capacitors are used for the dc-dc. The system achieves 7.9% energy reduction at the minimum energy point simultaneously with a 36.4% energy-delay product decrease and a 15% increase in dc-dc efficiency. In addition, the effect of local variations on average system performance is reduced by 12%.

Effects of back-gate bias on switched-capacitor DC-DC converters in UTBB FD-SOI

This paper explores the effects of back-gate bias on switched-capacitor (SC) DC-DC converters in 28 nm UTBB FD-SOI. By using back-gate bias to optimize the control circuitry and switches, the SC converter can operate with a peak efficiency of 72% in sleep mode (100 nW load) and 83% in active mode (100 μW load).

A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads

We introduce a fully integrated step-down self-oscillating switched-capacitor DC-DC converter that delivers near-threshold (NT) output voltages. The converter is built in 28 nm UTBB FD-SOI and occupies 0.0104 mm2. Back-gate biasing is utilized to increase the load power range. Measurements show a peak efficiency of 87%, self start-up capability, and a minimum efficiency of 75% for 79 nW to 200 μW (ideal) loads. Measurements with an off-chip NT processor load also show high efficiency. The converters large load power range and high efficiency are a good fit for energy-constrained NT processors.

A 5.3 pJ/op approximate TTA VLIW tailored for machine learning

To achieve energy efficiency in the Internet-of-Things (IoT), more intelligence is required in the wireless IoT nodes. Otherwise, the energy required by the wireless communication of raw sensor data will prohibit battery lifetime, the backbone of IoT. One option to achive this intelligence is to implement a variety of machine learning algorithms on the IoT sensor instead of the cloud. Shown here is sub-milliwatt machine learning accelerator operating at the Ultra-Low Voltage Minimum-Energy Point. The accelerator is a Transport Triggered Architecture (TTA) Application-Specific Instruction-Set Processor (ASIP) targeted for running various Machine Learning algorithms. The ASIP is implemented in 28nm FDSOI (Fully Depleted Silicon On Insulator) CMOS process, with an operating voltage of 0.35V, and is capable of 5.3pJ/cycle and 1.8nJ/iteration when performing conventional machine learning algorithms. The ASIP also includes hardware and compiler support for approximate computing. With the machine learning algorithms, computing approximately brings a maximum of 4.7% energy savings.

Minimum-energy point design in FDSOI Regular-V t

FDSOI has been shown to achieve extremely high performance at low operating voltages: a use-case extremely well suited for applications such as mobile processing. In IoT and Dark Silicon, use cases with extremely low application active times per standby times can be found. Investigated here are the turnover points where the higher threshold voltage and longer channel length options of FDSOI should be used. It was found that for activity factors below 3.2% to 0.5%, depending on the voltage, the Regular VT option of FDSOI should be used.

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.