Matthew Turnquist

Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery

We introduce an ultra-low-energy system comprised of a prototype 1.55V Li-ion battery, fully integrated switched-capacitor (SC) DC-DC 3:1 converter, and a 32-bit RISC CPU with timing-error prevention (TEP). The DC-DC converter and CPU are manufactured in 28nm UTBB FD-SOI. The DC-DC converter uses the batterys flat discharge curve and low nominal voltage to achieve a peak efficiency of 85%. The CPU operates from 0.3V-0.5V and with energy as low as 4.9pJ/cyc. The battery, DC-DC converter, and CPU system is able to operate with an average energy of 8pJ/cyc over 95% of the batterys discharge curve in the temperature range of -20oC to 70oC.

Rethinking DC-DC converter design constraints for adaptable systems that target the minimum-energy point

This paper explores a new DC-DC converter design constraint for adaptable systems that target the minimum-energy point (MEP). Traditionally, DC-DC converters have regulated to a fixed output voltage over a wide range of input voltages. For energy-constrained systems that target the MEP, regulating them to a fixed voltage is unnecessary since changes in the output voltage near the MEP have little impact on the energy per cycle. This paper applies a new and traditional design constraint to a 3:1 series-parallel switched-capacitor (SC) DC-DC converter in 28 nm CMOS. The new design constraint allows for decreased design time, less area, and less system-level energy per cycle compared to traditional constraints.

Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL

Timing error detection (TED) microprocessors are able to eliminate large timing margins by operating up to a voltage-frequency point in which intermittent errors occur. The detection of these errors requires an error-detection sequential (EDS) circuit. This paper presents the measurements of an EDS circuit called TEDsc. Using subthreshold source-coupled logic, TEDsc is able to dynamically adapt to system-level requirements. Measurements of TEDsc are presented in terms of a new system-level TED definition. TEDsc is implemented in 65 nm CMOS, has an area of 97.5 µm2, and consumes 79 pW (Vdd=250 mV). TEDsc operates at a clock period (TCLK) of 150 F04 at Vdd=400 mV with a sufficiently large detection window. By decreasing the size of the detection window, TEDsc can operate to at least TCLK=50 F04.

Implementing Minimum-Energy-Point Systems With Adaptive Logic

Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. This paper shows that the increased adaptability can be a great advantage in the system design in addition to the well-known mitigated susceptibility to ambient and internal variations. Specifically, the design tolerances of the power management are relaxed to enable even greater system-level energy savings than what can be achieved in the logic alone. In addition, the system is simultaneously able to operate near the minimum error point. Here, the power management is a simplified dc-dc converter and the TED is based on time borrowing. The target application is a single-chip system on chip without external discrete components; thus, switched capacitors are used for the dc-dc. The system achieves 7.9% energy reduction at the minimum energy point simultaneously with a 36.4% energy-delay product decrease and a 15% increase in dc-dc efficiency. In addition, the effect of local variations on average system performance is reduced by 12%.

Effects of back-gate bias on switched-capacitor DC-DC converters in UTBB FD-SOI

This paper explores the effects of back-gate bias on switched-capacitor (SC) DC-DC converters in 28 nm UTBB FD-SOI. By using back-gate bias to optimize the control circuitry and switches, the SC converter can operate with a peak efficiency of 72% in sleep mode (100 nW load) and 83% in active mode (100 μW load).

A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads

We introduce a fully integrated step-down self-oscillating switched-capacitor DC-DC converter that delivers near-threshold (NT) output voltages. The converter is built in 28 nm UTBB FD-SOI and occupies 0.0104 mm2. Back-gate biasing is utilized to increase the load power range. Measurements show a peak efficiency of 87%, self start-up capability, and a minimum efficiency of 75% for 79 nW to 200 μW (ideal) loads. Measurements with an off-chip NT processor load also show high efficiency. The converters large load power range and high efficiency are a good fit for energy-constrained NT processors.

Adaptive subthreshold timing-error detection 8 bit microcontroller in 65 nm CMOS

Subthreshold voltage operation enables digital systems to operate at ultra-low energy levels. However, as the voltage is reduced into subthreshold, the required safety margins become unrealistically large due to exponential dependencies. These margins can be addressed in a system by sensors, replica-path circuits, or timing error detection (TED). Each of these methods require additional energy overhead. TED is the only method that accounts for both global and local variations. This paper presents the first TED 8 bit microcontroller that is able to operate in subthreshold. The microcontroller uses adaptable EDS circuits to adjust to system-level constraints. It is built in 65 nm CMOS, uses 10.42 pJ/instruction, occupies an area of 50,200 μm2, and operates down to 300 mV.

Subthreshold timing error detection performance analysis

Timing error detection (TED) is a method in which setup timing errors are detected during run-time. When a violation is found, the system reacts on it to prevent error propagation. Incorporating TED circuits to a design introduces overhead. Thus, understanding how to efficiently implement TED with respect to the design constraints is a key issue. In this paper we compare energies of a conventional design to a TED design using different logic styles with different logic imbalances to investigate the energy difference between the designs in subthreshold operation region. TED mitigates variation problems introduced by using subthreshold operation, which is discussed. Using a 65 nm CMOS process, four different blocks have been simulated and analyzed, and subthreshold energy curves based on the forementioned are presented. The results indicate possibility for energy saving by utilizing TED.

Minimum-energy point design in FDSOI Regular-V t

FDSOI has been shown to achieve extremely high performance at low operating voltages: a use-case extremely well suited for applications such as mobile processing. In IoT and Dark Silicon, use cases with extremely low application active times per standby times can be found. Investigated here are the turnover points where the higher threshold voltage and longer channel length options of FDSOI should be used. It was found that for activity factors below 3.2% to 0.5%, depending on the voltage, the Regular VT option of FDSOI should be used.

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.