Mikko Kaltiokallio

Capacitive Coupling Element Antennas for Multi-Standard Mobile Handsets

Antenna prototypes based on a simple capacitive coupling element (CCE) on a compact smartphone chassis are presented. This versatile antenna structure is easily modifiable with circuit design. We show with experimental data how the same CCE is implemented first with single-feed and then with dual-feed interface towards the transceiver front-end. These two antennas operate at the LTE-A frequencies 698–960 MHz and 1710–2690 MHz with good efficiency, owing to a novel dual-branch impedance matching circuit which utilizes the properties of the CCE and the chassis in a proficient way. A third antenna based on the same CCE is designed for a software defined radio receiver. This tunable antenna operates at 750–2500 MHz with acceptable efficiency.

A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver

An integrated fifth-order continuous-time low-pass filter for a WiMedia ultrawideband radio receiver is described in this paper. The prototype filter is realized with a passive pole at the filter input and a fourth-order leapfrog filter in which the gm-C technique with pseudodifferential transconductors is used. The transconductors do not include internal nodes, and they are designed to have a nominal 26-dB dc gain, of which process, voltage, and temperature variations are controlled by means of a negative resistance circuit. The losses of the low-dc-gain filter integrators are already taken into account in the filter synthesis. The passband edge frequency of the implemented filter is 240 MHz in order to receive multiband-orthogonal-frequency-division-multiplexing signals using the direct-conversion topology. The voltage gain of the filter can be controlled from 9 to 43 dB in the 1-dB gain steps. The filter achieves a 7.8-nVradicHz input-referred noise density, a -8-dBV out-of-band third-order intermodulation intercept point, and a +15-dBV out-of-band second-order intermodulation intercept point. The circuit uses a 1.2-V supply and has been fabricated in a modern 65-nm CMOS technology.

A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver

A 240MHz 5th-order gm-C low-pass filter for WiMedia UWB system is presented. The filter uses a 1.2V supply and is fabricated in 0.13mum CMOS. The filter is targeted for a direct-conversion radio receiver and is based on precise-gain filter synthesis. It includes gain control from 13 to 48dB in 1dB steps. The filter achieves an input-referred noise of 7.7nV/radicHz, an out-of-band IIP3 of -8.2dBV and consumes 24mW

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

A 60-GHz CMOS receiver with an on-chip ADC

A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is −38.5 dBm.

Wideband 2 to 6 GHz RF Front-End With Blocker Filtering

This paper presents a wideband blocker filtering technique for an RF front-end. A wideband LNA and a transferred impedance filter are implemented as part of a receiver to demonstrate the feasibility of the system. The transferred impedance filter includes an adjustable polyphase filter to compensate for the phase shift in the system in order to maintain correct operating frequency. The transferred impedance filter with passive mixers and the wideband LNA are analyzed by means of frequency transformation to demonstrate the different design trade-offs. The front-end achieves a gain of 43 and 41 dB and a noise figure of 3.2 and 5.7 dB with an IIP3 of -13 and -5 dBm with the transferred-impedance filter turned off and on, respectively. An added selectivity of 6 dB is achieved by using the solutions described in this paper.

A 2.5-GHz Receiver Front-End With Q-Boosted Post-LNA N-Path Filtering in 40-nm CMOS

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of > 0 dBm, while consuming 48 mA from a 1.1-V supply.

A 0.7–2.7-GHz Blocker-Tolerant Compact-Size Single-Antenna Receiver for Wideband Mobile Applications

Passive-mixer-first receivers have recently demonstrated flexible, low-noise, and high-linearity performance. Likewise, capacitive coupling element antennas have been demonstrated to be a viable choice for mobile handset integration. This paper combines these two advances into a single-antenna wideband receiver that achieves a 0.7-2.7-GHz reception band. The compact-size wideband tunable antenna achieves an efficiency of 45%-69% and occupies a volume of 2500 mm3. The front-end integrated circuit achieves an input compression point of +5 dBm with a noise figure of 4 dB while occupying only 0.3 mm2 of active die area. Additionally, an interface impedance study is performed to find the optimal impedances around the passive mixer and to demonstrate the different design tradeoffs of a passive-mixer-first receiver. A local oscillator duty-cycle adjustment circuit and its effect on the receiver performance is also presented.

A WiMedia UWB receiver with a synthesizer

This paper describes a direct-conversion receiver for WiMedia UWB applications. The receiver consists of separate BG1 and BG3 LNAs including a 2.4-GHz notch filter, quadrature mixers, a base-band gm-C low-pass filter with variable gain, and a fast-hopping synthesizer. The UWB receiver is targeted for a mobile handset and therefore special emphasis has been placed on the reduction of interferers. The receiver achieves 60-dB gain, noise figure less than 6.2 dB, LO settling time of less than 3 ns and DC current consumption of 137 mA from a 1.2-V supply for BG1 operation mode. The chip was fabricated using 65-nm standard CMOS process.

A wideband interference tolerant RF receiver for cognitive radio sensor unit

A wideband receiver for cognitive radio spectrum sensing unit is presented. The circuit consists of a high linearity low noise amplifier, passive mixer, and baseband buffer. IQ signals for the LO are generated using a divide-by-two circuit. Low noise amplifier includes common-gate common-source combination for simultaneous interference suppression and noise canceling. The receiver operates in the LTE bands at 0.7 - 2.6 GHz, with typical performance of 32 dB gain, 5 dB noise figure, and IIP3 linearity between 5 dBm and -1 dBm in the LTE bandwidth. The circuit is designed for 65-nm CMOS technology.