Markus M. Helms

Formal verification made easy

Formal verification (FV) is considered by many to be complicated and to require considerable mathematical knowledge for successful application. We have developed a methodology in which we have added formal verification to the verification process without requiring any knowledge of formal verification languages. We use only finite-state machine notation, which is familiar and intuitive to designers. Another problem associated with formal verification is state-space explosion. If that occurs, no result is returned; our method switches to random simulation after one hour without results, and no effort is lost. We have compared FV against random simulation with respect to development time, and our results indicate that FV is at least as fast as random simulation. FV is superior in terms of verification quality, however, because it is exhaustive.

IBM system z10 I/O subsystem

The performance, reliability, and functionality of a large server are greatly influenced by the design characteristics of its I/O subsystem. The critical components of the IBM System z10™ I/O subsystem have, therefore, been significantly improved in terms of performance, capability, and cost. The first-order network has been redesigned from the long-evolved enhanced self-timed interface (eSTI) links to utilize InfiniBand™ links. A redesign of the host logic of I/O chips and the fiberoptic interfaces within the links made it possible to introduce InfiniBand-based IBM Parallel Sysplex® links. A broad range of legacy I/O channels have been carried forward to connect through InfiniBand, and a foundation has been laid for new channel types of improved functionality and performance. The first such hardware channel to be introduced is the next generation of Ethernet-virtualization data routers. A new and methodical recovery structure has been designed to ensure consistent, extensive support of reliability, availability, and serviceability. A building-block-oriented design process has been developed to enable the innovations that made these advances possible. Finally, a new performance verification methodology has been introduced to ensure that the system and subsystem designs are balanced to make effective use of the increased capacity.

The structure of chips and links comprising the IBM eServer z990 I/O subsystem

The performance of large servers is to a high degree determined by their I/O subsystems. In the z990 server, nearly all of the components in the I/O path have been considerably improved in performance, capability, and cost. A 2-GB/s enhanced self-timed interface (eSTI) was introduced which is capable of absorbing the ever-increasing data rates of modern high-speed adapters. The I/O bandwidth available from a single node (three memory bus adapter, or MBA, chips, each with four eSTI ports) now equals 48 GB/s. As a consequence, both the MBA chip and the STI multiplexer switch (STI switch) chip had to be completely redesigned. In addition to these two chips, this paper describes the eSTI design itself and the Sweep chip, which integrates the function of four bidirectional adapter chips, one switch chip, and a clock chip.

The IBM z13 multithreaded microprocessor

The IBM z13™ system is the latest generation of the IBM z Systems™ mainframes. The z13 microprocessor improves upon the IBM zEnterprise® EC12 (zEC12) processor with two vector execution units, higher instruction execution parallelism, and a simultaneous multithreaded (SMT) architecture that supports concurrent execution of two threads. These advances yield performance gains in legacy online transaction processing and business analytics workloads. This latest generation system features an eight-core processor chip, a robust cache hierarchy, and large multiprocessor system design optimized for enterprise database and transaction processing workloads. The microprocessor core features a wide super-scalar, out-of-order pipeline that can sustain an instruction fetch, decode, dispatch, and completion rate of six z/Architecture® instructions per cycle. The instruction execution path is predicted by multi-level branch direction and target prediction logic. Complex instructions are split into two or more simpler micro-operations. Instructions are issued out of program order from an instruction issue queue to multiple RISC (reduced instruction set computer) execution units. The super-scalar design can sustain an issue and execution rate of ten micro-operations per cycle: two load/store type instructions, four fixed point (integer) instructions, two floating point or vector instructions, and two branch instructions.

Event monitoring in a system-on-a-chip

This paper presents a novel approach for monitoring disjunct, concurrent operations in heavily queued systems. A non-obtrusive activity monitor is used as an on-chip tracing unit. For each pending operation the monitor uses the hardware implementation of an event triggered operation graph to trace the path of the operation through the system. Other than conventional tracing units that collect and record information from one or more functional units for later analysis, the presented solution directly records the path of the operation through the system, enabling an immediate analysis of operation inconsistencies. For each followed path a unique signature is generated that significantly reduces the amount of trace data to be stored. The trace information is stored together with a time stamp for debugging and measuring of queuing effects and timing behavior in the system. The presented method has been successfully applied to an IO-Adapter-chip in IBMs S/390 G5 and G6 Systems.

Design and verification of the IBM system z10 I/O subsystem chips

In this paper, we discuss the microarchitecture, design, and S. Junghans verification of two IBM System z10™ I/O (input/output) chips: the z10™ hub chip, an InfiniBand™ host channel adapter with IBMproprietary enhancements, and the InfiniBand memory bus adapter (MBA) chip, an InfiniBand-to-self-timed-interface fanout chip for attaching legacy I/O. Designing and verifying these chips presented many challenges. We describe our transaction- and packet-tracking concepts and the use of communication groups that emulate the behavior of logical partitions and their role in handling error and recovery cases. A novel technique has been employed to ensure that design implementation and architectural register definitions are consistent in a fully automated approach. Finally, we describe our approach to improving self-test coverage, which is based on an automated process of test-point insertion.

An easy approach to formal verification

Formal verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds formal verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.

IBM Parallel Sysplex design for the IBM z196 system

The coupling adapter hub of an IBM System z® server is a key component for the IBM System z Parallel Sysplex®. The hub is built to exchange messages between systems in a highly efficient manner. This paper describes the latest generation of high-fanout and low-latency coupling adapter cards, the associated firmware, and a new protocol. As in the z10® system, there is a long-range and a short-distance card. The coupling adapter for zEnterprise® 196 (z196) is based on the z10 infrastructure (InfiniBand® link layer), with the internal transport engine for message handling completely redesigned to support the new protocol and improve connectivity, latency, and throughput. In addition to enabling the new adapters functionality, the Parallel Sysplex support firmware has several significant enhancements in a number of functional areas. Connectivity and utilization are improved through the ability to define more channels and more concurrent connections (message buffer sets) for each channel. Through a combination of hardware and firmware protocols, response time for messages at a short distance is significantly improved. Finally, new methods are presented that support efficient presilicon and postsilicon functional and performance verification.

Event monitoring in highly complex hardware systems

This paper presents a novel approach for monitoring disjunct, concurrent operations in heavily queued systems. A nonobtrusive activity monitor is used as an on-chip tracing unit. For each pending operation the monitor uses the hardware implementation of an event-triggered operation graph to trace the path of the operation through the system. In contrast to conventional tracing units, which collect and record information from one or more functional units for later analysis, the presented solution directly records the path taken by the operation through the system, making possible an immediate analysis of operation inconsistencies. For each followed path a unique signature is generated which significantly reduces the amount of trace data to be stored. The trace information is stored together with a time stamp for debugging and measuring of queueing effects and timing behavior in the system. The method presented has been successfully applied to the memorybus adapter chips in the S/390® G5 and G6 systems.