Rolf Fritz

Formal verification made easy

Formal verification (FV) is considered by many to be complicated and to require considerable mathematical knowledge for successful application. We have developed a methodology in which we have added formal verification to the verification process without requiring any knowledge of formal verification languages. We use only finite-state machine notation, which is familiar and intuitive to designers. Another problem associated with formal verification is state-space explosion. If that occurs, no result is returned; our method switches to random simulation after one hour without results, and no effort is lost. We have compared FV against random simulation with respect to development time, and our results indicate that FV is at least as fast as random simulation. FV is superior in terms of verification quality, however, because it is exhaustive.

Event monitoring in a system-on-a-chip

This paper presents a novel approach for monitoring disjunct, concurrent operations in heavily queued systems. A non-obtrusive activity monitor is used as an on-chip tracing unit. For each pending operation the monitor uses the hardware implementation of an event triggered operation graph to trace the path of the operation through the system. Other than conventional tracing units that collect and record information from one or more functional units for later analysis, the presented solution directly records the path of the operation through the system, enabling an immediate analysis of operation inconsistencies. For each followed path a unique signature is generated that significantly reduces the amount of trace data to be stored. The trace information is stored together with a time stamp for debugging and measuring of queuing effects and timing behavior in the system. The presented method has been successfully applied to an IO-Adapter-chip in IBMs S/390 G5 and G6 Systems.

An easy approach to formal verification

Formal verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds formal verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.

Event monitoring in highly complex hardware systems

This paper presents a novel approach for monitoring disjunct, concurrent operations in heavily queued systems. A nonobtrusive activity monitor is used as an on-chip tracing unit. For each pending operation the monitor uses the hardware implementation of an event-triggered operation graph to trace the path of the operation through the system. In contrast to conventional tracing units, which collect and record information from one or more functional units for later analysis, the presented solution directly records the path taken by the operation through the system, making possible an immediate analysis of operation inconsistencies. For each followed path a unique signature is generated which significantly reduces the amount of trace data to be stored. The trace information is stored together with a time stamp for debugging and measuring of queueing effects and timing behavior in the system. The method presented has been successfully applied to the memorybus adapter chips in the S/390® G5 and G6 systems.