Manfred Walz

The structure of chips and links comprising the IBM eServer z990 I/O subsystem

The performance of large servers is to a high degree determined by their I/O subsystems. In the z990 server, nearly all of the components in the I/O path have been considerably improved in performance, capability, and cost. A 2-GB/s enhanced self-timed interface (eSTI) was introduced which is capable of absorbing the ever-increasing data rates of modern high-speed adapters. The I/O bandwidth available from a single node (three memory bus adapter, or MBA, chips, each with four eSTI ports) now equals 48 GB/s. As a consequence, both the MBA chip and the STI multiplexer switch (STI switch) chip had to be completely redesigned. In addition to these two chips, this paper describes the eSTI design itself and the Sweep chip, which integrates the function of four bidirectional adapter chips, one switch chip, and a clock chip.

IBM Enterprise System/900 Type 9121 system controller and memory subsystem design

A system controller supporting two processors, two independent memory banks, and a channel subsystem has been implemented within a single air-cooled thermal conduction module for the IBM Enterprise System/9000™ Type 9121 processors. Improvements in technology densities, usage of CMOS and emitter-coupled logic on the same substrate, and innovations in the system controller design were required to achieve the one-module objective. In addition, system reliability is improved with a storage key error-correction code, and storage allocation options are increased with a combined main/expanded store design. In conjunction with the system controller development, a new memory subsystem has been designed for the 9121 system. Innovative large-system memory packaging techniques and functional changes in the data accessing methods have culminated in a memory board which supports up to one-gigabyte system storage.

Event monitoring in a system-on-a-chip

This paper presents a novel approach for monitoring disjunct, concurrent operations in heavily queued systems. A non-obtrusive activity monitor is used as an on-chip tracing unit. For each pending operation the monitor uses the hardware implementation of an event triggered operation graph to trace the path of the operation through the system. Other than conventional tracing units that collect and record information from one or more functional units for later analysis, the presented solution directly records the path of the operation through the system, enabling an immediate analysis of operation inconsistencies. For each followed path a unique signature is generated that significantly reduces the amount of trace data to be stored. The trace information is stored together with a time stamp for debugging and measuring of queuing effects and timing behavior in the system. The presented method has been successfully applied to an IO-Adapter-chip in IBMs S/390 G5 and G6 Systems.

Design and verification of the IBM system z10 I/O subsystem chips

In this paper, we discuss the microarchitecture, design, and S. Junghans verification of two IBM System z10™ I/O (input/output) chips: the z10™ hub chip, an InfiniBand™ host channel adapter with IBMproprietary enhancements, and the InfiniBand memory bus adapter (MBA) chip, an InfiniBand-to-self-timed-interface fanout chip for attaching legacy I/O. Designing and verifying these chips presented many challenges. We describe our transaction- and packet-tracking concepts and the use of communication groups that emulate the behavior of logical partitions and their role in handling error and recovery cases. A novel technique has been employed to ensure that design implementation and architectural register definitions are consistent in a fully automated approach. Finally, we describe our approach to improving self-test coverage, which is based on an automated process of test-point insertion.

Event monitoring in highly complex hardware systems

This paper presents a novel approach for monitoring disjunct, concurrent operations in heavily queued systems. A nonobtrusive activity monitor is used as an on-chip tracing unit. For each pending operation the monitor uses the hardware implementation of an event-triggered operation graph to trace the path of the operation through the system. In contrast to conventional tracing units, which collect and record information from one or more functional units for later analysis, the presented solution directly records the path taken by the operation through the system, making possible an immediate analysis of operation inconsistencies. For each followed path a unique signature is generated which significantly reduces the amount of trace data to be stored. The trace information is stored together with a time stamp for debugging and measuring of queueing effects and timing behavior in the system. The method presented has been successfully applied to the memorybus adapter chips in the S/390® G5 and G6 systems.