Marleen Ade

Grape-II: a system-level prototyping environment for DSP applications

We propose a rapid-prototyping setup to minimize development cost and a structured-prototyping methodology to reduce programming effort. The general-purpose hardware consists of commercial DSP processors, bond-out versions of core processors, and field-programmable gate arrays (FPGAs) linked to form a powerful, heterogeneous multiprocessor, such as the Paradigm RP developed within the Retides (Real-Time DSP Emulation System) Esprit project. Our Graphical Rapid Prototyping Environment (Grape-II) automates the prototyping methodology for these hardware systems by offering tools for resource estimation, partitioning, assignment, routing, scheduling, code generation, and parameter modification. Grape-II has been used successfully in three real-world DSP applications. >

Hardware-software codesign with GRAPE

GRAPE-II (Graphical Rapid Prototyping Environment-II) is a hardware-software codesign environment for the real-time functional emulation of synchronous DSP systems. It allows one to specify the applications data dependency graph in a target-machine-independent way. After specifying the heterogeneous target machines architecture, it estimates the resources needed by each application subtask. Based on these requirements, it assigns the subtasks to specific target devices at compile-time, be they processors or FPGAs, establishes routing paths and determines a static schedule. It generates a main shell for each target device and generates intra-device and inter-device communication code. After downloading the executable images on to the target machine, it allows the designer to modify end-user controls and application settings at run-time. This paper situates the tool in the application design cycle, explains GRAPE-IIs design flow and shows the advantages of hardware-software codesign by evaluating the achievable sampling frequency for a small example application.

Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets

The paper presents an algorithm to determine the close-to-smallestpossible data buffer sizes for arbitrary synchronous dataflow (SDF) applications, such that we can guarantee the existenceof a deadlock free schedule. The presented algorithm fits inthe design flow of GRAPE, an environment for the emulation andimplementation of digital signal processing (DSP) systems onarbitrary target architectures, consisting of programmable DSPprocessors and FPGAs. Reducing the size of data buffers is ofhigh importance when the application will be mapped on FieldProgrammable Gate Arrays (FPGA), since register resources arerather scarce.

Geometric parallelism and cyclo-static data flow in GRAPE-II

Describes two novel features that are supported in GRAPE-II (Graphical RApid Prototyping Environment): geometric parallelism and cyclo-static data flow. GRAPE-II is intended as a system level tool for the rapid prototyping of digital signal processing (DSP) applications on multiprocessors. GRAPE-II fully supports code generation for multi-rate and asynchronous DSP applications on heterogeneous target multiprocessors. The first feature detailed in the paper, geometric parallelism, allows the programmer to efficiently specify data parallel operations, where multiple identical functions operate on different data sets. The second feature, cyclo-static data flow, enables the specification of cyclicly changing data dependencies, while still leading to static schedules.<<ETX>>

Buffer memory requirements in DSP applications

Studies synchronous multi-rate data flow graphs to determine the minimal required buffer sizes that still guarantee the construction of a deadlock-free static schedule. We develop a rule to quickly analyze a graphs consistency. A graph is split up into single and parallel paths. Single paths are analysed, as well as the most frequent parallel paths. The results are used in the rapid prototyping environment GRAPE-II in the case where the emulation hardware contains FPGAs, or when memory is critical.<<ETX>>

Code generation of data dominated DSP applications for FPGA targets

The VHDL code generator of the GRAPE rapid prototyping and design environment has been extended to support a much wider range of data dominated applications. We describe the approach taken to implement CSDF applications on FPGAs, including the automatic code generation for task communication and scheduling on FPGAs alone or in conjunction with DSP processors. The implementation choices are discussed, and a comparison to manual code generation is made.

Code generation for compiled bit-true simulation for DSP application

Bit-true simulation verifies the finite word length choices in the VLSI implementation of a DSP application. Present-day bit-true simulation tools are time consuming. We elaborate a new approach in which the signal flow graph of the application is analyzed and then transformed utilizing the flexibility available on the simulation target. This global approach outperforms current tools by an order of magnitude in simulation time.

Implementing DSP applications on heterogeneous targets using minimal size data buffers

The paper presents an algorithm to determine the smallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the existence of a deadlock free schedule. The presented algorithm fits in the design flow of GRAPE, an environment for the emulation and implementation of digital signal processing (DSP) systems on arbitrary target architectures, consisting of programmable DSP processors and FPGAs. Reducing the size of data buffers is of high importance when the application will be mapped on Field Programmable Gate Arrays (FPGA), since register resources are rather scarce.

Transformations of a 3D image reconstruction algorithm for data transfer and storage optimisation

When implementing a 3D image reconstruction algorithm on a DSP architecture, we find ourselves confronted with a large memory transfer overhead, reducing the possible speedup attainable on recent multi-media oriented architectures. This paper describes how the critical part of the algorithm is re-specified and aggressively transformed at the algorithm code level, to improve the data access locality of the multi-dimensional image signal, while preserving the input/output behaviour. Experiments show that a close to optimal reuse of the data in the foreground memory and registers is obtained, removing the data transfer and storage bottleneck and enabling real-time prototyping of the algorithm on a DSP architecture.

Hardware-software trade-offs for emulation

The author discuss the hardware versus software trade-offs for the functional and bit-compliant emulation of digital systems. They consider two classes of components: processors (software emulation) and field programmable gate arrays (hardware emulation). In a case study, a neural exclusive-or function is emulated on both platforms. This leeds to the conclusion that many applications will need a heterogeneous emulation environment.<<ETX>>