Martijn T. Bennebroek

A novel toolset for the development of FPGA-like reconfigurable logic

This paper introduces a toolset to develop FPGA-like reconfigurable logic which is optimized towards a specific application domain. Compared to existing multi-domain architectures, domain-optimized reconfigurable logic carry much lower area costs and, therefore, might drive the deployment of embedded FPGA-like cores in integrated circuits. An architectural template has been developed that enables the definition of components with a virtually unmatched flexibility. The toolset provides fast feedback on the effect of architectural changes upon mapping results. Once satisfactory optimized, the architecture can actually be implemented in a selected CMOS process technology and, besides soft- and hard- cores, patterns for manufacturing test are generated. Special attention is given to the developed graphical architecture editor and place-and-route tool. An example is included to demonstrate the toolset usage and the advantages of the flexible component definitions. Here, the routing network of a simple architecture is optimized for a set of functions from the MCNC benchmark set and the result compares favorable to that obtained by VPR.

Energy-Efficient FPGA Interconnect Design

Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size, performance, and/or energy consumption. In this paper, we address the latter bottleneck and propose a novel FPGA interconnect architecture that reduces energy consumption without sacrificing performance and size. It is demonstrated that the delay of a full-swing, fully-buffered interconnect architecture can be matched by a low-swing solution that dissipates significantly less power and contains a mix of buffer and pass-gate switches. The actual energy savings depend on the specifics of the interconnect design and applications involved. For the considered fine-grain FPGA example, energy savings are observed to range from a factor 4.7 for low-load critical nets to a factor 2.8 for high-load critical nets. The results are obtained from circuit simulations in a 0.13mum CMOS technology for various benchmarks

Low-complexity R-peak detection in ECG signals: A preliminary step towards ambulatory fetal monitoring

Non-invasive fetal health monitoring during pregnancy has become increasingly important. Recent advances in signal processing technology have enabled fetal monitoring during pregnancy, using abdominal ECG recordings. Ubiquitous ambulatory monitoring for continuous fetal health measurement is however still unfeasible due to the computational complexity of noise robust solutions. In this paper an ECG R-peak detection algorithm for ambulatory R-peak detection is proposed, as part of a fetal ECG detection algorithm. The proposed algorithm is optimized to reduce computational complexity, while increasing the R-peak detection quality compared to existing R-peak detection schemes. Validation of the algorithm is performed on two manually annotated datasets, the MIT/BIH Arrhythmia database and an in-house abdominal database. Both R-peak detection quality and computational complexity are compared to state-of-the-art algorithms as described in the literature. With a detection error rate of 0.22% and 0.12% on the MIT/BIH Arrhythmia and in-house databases, respectively, the quality of the proposed algorithm is comparable to the best state-of-the-art algorithms, at a reduced computational complexity.

Low energy FPGA interconnect design

FPGAs are not energy efficient largely due to their programmable, capacitively loaded interconnect. We propose a new low energy FPGA interconnect architecture that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study, based on circuit simulations using SPICE in CMOS 0.13 micron process technology, illustrates that a 41% energy reduction can be achieved compared to the conventional techniques. A one to one comparison between NMOS based switches and the proposed DTMOS based switches reveal that the latter have a 36% lower power-delay product. We also show through a model analysis and circuit simulations that using low swing on interconnect, a timing budget can be met at 30% less energy consumption.

A dual-core system solution for wearable health monitors

This paper presents a system design study for wearable sensor devices intended for healthcare and lifestyle applications based on ECG, EEG and activity monitoring. In order to meet the low-power requirement of these applications, a dual-core signal processing system is proposed which combines an ultra-low-power bio-medical Application Specific Instruction-set Processor (BioASIP) and a low-power general-purpose micro-controller (MSP430). To validate the merits of the proposed architecture, system-level power analysis and trade-offs are conducted using real hardware measurements of an ECG R-peak detection application. The results show that the proposed dual-core architecture consumes around 65.38µW, about 25.8x smaller than an MSP430-only approach. Out of 65.38µW, the BioASIP consumes only 11µW and the rest is used in the analog front-end, A/D conversion, and control tasks.

Deployment of wireless sensors for remote elderly monitoring

The FP6 project “Wireless Accessible Sensor Populations” (WASP) has developed an end-to-end infrastructure for the deployment and enterprise integration of wireless sensor nodes. The infrastructure is generic and allows for optimisation for a variety of applications by the development of dedicated services that can be distributed over (wearable and ambient) sensor nodes, the WSN gateway, and the enterprise (backend) system. Key to many applications, such as elderly care considered in this paper, is to optimise the battery lifetime of wearable sensor nodes that can be (remotely) customized to the monitoring needs of individual persons and to the quality-of-service demands for offered services. The WASP infrastructure provides practical solutions for these targets and is being validated for realistic elderly care scenarios. These scenarios aim to support the elderly in (semi-) independent Ambient Assisted Living settings as well as to provide health workers with effective means of studying transient deterioration and behavior changes characteristic to the ageing population.

Astra: An Advanced Space-Time Reconfigurable Architecture

This paper introduces ASTRA, a novel FPGA-like architecture that can perform operations in space (for maximum performance) or in time (for minimum hardware area) at logic-cell level. Currently, ASTRA is tailored towards DSP applications and supports data flow between nearest neighbor cells. Control signals can be distributed over longer distances using bus-like connections. ASTRAs (logic and interconnect) silicon area is shown to be quite low while still providing sufficient flexibility for real-life applications. First benchmarking results with traditional applications from DSP domain show that ASTRA is competitive with respect to ASIC in terms of silicon area and power consumption

Multiplexer-Based Routing Fabric for Reconfigurable Logic

A novel routing fabric is introduced that offers high flexibility at significant lower silicon cost compared to routing fabrics currently incorporated in many field programmable gate array (FPGA) devices, IP cores, and IP-core wrappers. The novel fabric is entirely constructed from multiplexers and unidirectional point-to-point connections, controlled by configuration bits, and prove very efficient when mapping applications. For a fabric connecting 4-input look-up-tables, area savings of 60% are demonstrated when routing applications from the MCNC benchmark set.

Wirelessly Accessible Sensor Populations (WASP): Deployment and Enterprise Integration of Energy-Efficient Wireless Sensor Networks

This paper provides an update of the WASP project, which is currently in its third year of execution. WASP project aims at narrowing down the gap between the academic research solutions for wireless sensor networks and their industrial usage. This poster abstract zooms in on two of the project activities namely a low-power traffic aware MAC protocol and a light weight service discovery protocol.

A novel routing architecture for field-programmable gate-arrays

A novel routing fabric is introduced that offers high flexibility at significantly lower silicon cost compared to routing fabrics currently incorporated in Field Programmable Gate Array (FPGA) devices, IP cores, and IP-core wrappers. This fabric is entirely constructed from multiplexers and unidirectional point-to-point connections, controlled by configuration bits. Key in optimizing its efficiency is to derive an appropriate connectivity pattern between logic blocks. Although this problem is complex in general, three guidelines have been identified to define suitable patterns. For a fabric connecting 4-input Look-Up-Tables, area savings of 60% are demonstrated when routing applications from the MCNC benchmark set. The use of multiplexer-based routing is not limited to these basic logic blocks only, so the potential of its usage for more complex logic blocks is illustrated as well. Benefits in timing closure, performance, and power are briefly discussed.