Alexander Danilin

Architecture and Applications of wireless Smart Cameras (Networks)

A network of (wireless smart) cameras can analyse the scene from different views. Wireless smart cameras challenge the hardware for low-power consumption and high imaging performance. In this paper we introduce a wireless smart camera based on an SIMD video-analysis processor and an 8051 microcontroller as a local host. Wireless communication is through the IEEE 802.15.4 standard. The camera constructed in this paper is to enable application research into distributed smart camera systems.

Real-time implementations of Hough Transform on SIMD architecture

Implementation of the Hough transform (HT) for line detection requires massive computation, large memory space and high bandwidth. Without parallel processing on a proper platform, it can be hardly implemented in real-time, especially with high accuracy on high-resolution images. This paper proposes several efficient methods for implementation of HT on SIMD (single-instruction, multiple-data) architecture. All lines in an image/frame can be detected in real time with the proposed voting method, the novel Hough space (HS) structures, and the efficient image ldquorotationrdquo mechanism. With suggested refinement and tracking approach, we can capture and follow the target lines with very high accuracy. Analysis and comparison are elaborated with real-time implementation on our wireless smart camera (WiCa) platform, which is a powerful image/video processing platform developed by NXP Semiconductors. Moreover, two different applications, lane detection and gesture control, are also developed on this platform.

Toward low latency gesture control using smart camera network

Real-world gesture controlled applications are not yet widely present mainly due to strong practical constraints. As a step toward realizing a practical, affordable, low-power, real time, low-latency gesture control, we present a smart camera system and an algorithm for upper body pose reconstruction implemented on the system. A single-instruction multiple-data (SIMD) processor on a smart camera platform is used to detect person head and hands. The detected hand and head candidate positions are then transmitted to a central processor (a PC) where the data is combined and final decisions are made. Implementation of a computer vision algorithm on the SIMD camera processor is presented. We also describe the whole wireless smart camera system and analyze the performance and practical issues.

Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration

In the first part of this paper, an improved slope-intercept like representation is proposed for implementation of Standard Hough Transform (SHT) on SIMD (Single-Instruction, Multiple-Data) architectures with no local indirect addressing support. The real-time implementation is realized with high accuracy on our Wireless Smart Camera (WiCa) platform. The processing time of this approach is independent of the number of edge points or the number of detected lines. In the second part, we focus on analyzing the differences between the SHT implementations on 1-D SIMD architectures with and without local indirect addressing. Three aspects are compared: total operation number, memory access/energy consumption, and memory area cost. When local indirect addressing is supported, the results show a considerable amount of reduction in total operations and energy consumption at the cost of extra chip area. The results also show that the focuses for further optimization of these two architectures are different.

Multiplexer-Based Routing Fabric for Reconfigurable Logic

A novel routing fabric is introduced that offers high flexibility at significant lower silicon cost compared to routing fabrics currently incorporated in many field programmable gate array (FPGA) devices, IP cores, and IP-core wrappers. The novel fabric is entirely constructed from multiplexers and unidirectional point-to-point connections, controlled by configuration bits, and prove very efficient when mapping applications. For a fabric connecting 4-input look-up-tables, area savings of 60% are demonstrated when routing applications from the MCNC benchmark set.

Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems

Application specific reconfigurable architectures are gaining increasing popularity. This paper introduces an application case of such an architecture in multi-standard interleaving and deinterleaving. Three different implementation options are presented and compared with each other in terms of area and flexibility.

A novel routing architecture for field-programmable gate-arrays

A novel routing fabric is introduced that offers high flexibility at significantly lower silicon cost compared to routing fabrics currently incorporated in Field Programmable Gate Array (FPGA) devices, IP cores, and IP-core wrappers. This fabric is entirely constructed from multiplexers and unidirectional point-to-point connections, controlled by configuration bits. Key in optimizing its efficiency is to derive an appropriate connectivity pattern between logic blocks. Although this problem is complex in general, three guidelines have been identified to define suitable patterns. For a fabric connecting 4-input Look-Up-Tables, area savings of 60% are demonstrated when routing applications from the MCNC benchmark set. The use of multiplexer-based routing is not limited to these basic logic blocks only, so the potential of its usage for more complex logic blocks is illustrated as well. Benefits in timing closure, performance, and power are briefly discussed.

A Novel Reconfigurable Architecture for Temporal and Spatial Application Mapping

This paper introduces a novel FPGA-like architecture that can perform operations in space (for maximum performance) or in time (for minimum hardware area) at logic-cell level. Based on our previous work concerning DSP applications mapping onto ASTRA reconfigurable architecture, this paper describes the microarchitecture in more detail and introduces some significant improvements. The silicon area of the logic tile is reduced by 40%. The area figures of the benchmarks are only factor 10-25 worse than the ASIC implementation - a very competitive ratio for a reconfigurable architecture.