Sergei Sawitzki

A novel toolset for the development of FPGA-like reconfigurable logic

This paper introduces a toolset to develop FPGA-like reconfigurable logic which is optimized towards a specific application domain. Compared to existing multi-domain architectures, domain-optimized reconfigurable logic carry much lower area costs and, therefore, might drive the deployment of embedded FPGA-like cores in integrated circuits. An architectural template has been developed that enables the definition of components with a virtually unmatched flexibility. The toolset provides fast feedback on the effect of architectural changes upon mapping results. Once satisfactory optimized, the architecture can actually be implemented in a selected CMOS process technology and, besides soft- and hard- cores, patterns for manufacturing test are generated. Special attention is given to the developed graphical architecture editor and place-and-route tool. An example is included to demonstrate the toolset usage and the advantages of the flexible component definitions. Here, the routing network of a simple architecture is optimized for a set of functions from the MCNC benchmark set and the result compares favorable to that obtained by VPR.

High-Throughput and Low-Power Architectures for Reed Solomon Decoder

This paper presents a uniform comparison between various algorithms and architectures used for Reed Solomon (RS) decoder. For each design option, a detailed hardware analysis is provided, in terms of gate count, latency and critical path delay. A new low-power syndrome computation is proposed in the paper. Dual-line architecture of modified Berlekamp Massey algorithm was chosen for Ultra Wide-band (UWB) as an application example. The results obtained are very encouraging both in terms of silicon area and power. A detailed analysis of results is presented and they are also compared with other published industrial and academic designs. I. INTRODUCTION Reed Solomon (RS) codes have been widely used in a variety of communication systems. Continual demand for ever higher data rates and storage capacity makes it necessary to devise very high-speed implementations of RS decoders. A number of algorithms are available and this often makes it difficult to determine the best choice due to the number of variables and trade-offs available. For IEEE 802.15-03 standard proposal (commonly known as UWB) in particular, very high data rates for transmission are needed. Since the standard is also meant for portable devices, power consumption is of prime concern. There is no clear algorithm or architecture that can meet the low-power and high-throughput requirements of UWB. In this paper, a uniform comparison of various designs and architecture is presented. Dual-line architecture of BerleKamp Massey algorithm was implemented, with a lot of other optimisations to the conventional design. In the next section we present an introduction to RS codes and the decoder structure, followed by syndrome computation architecture. The design space is explored in the following section. We then present the results obtained for the archi- tecture chosen for UWB followed by some optimisations to the design. The results are then compared with existing architectures in the section on benchmarking followed by conclusions.

Astra: An Advanced Space-Time Reconfigurable Architecture

This paper introduces ASTRA, a novel FPGA-like architecture that can perform operations in space (for maximum performance) or in time (for minimum hardware area) at logic-cell level. Currently, ASTRA is tailored towards DSP applications and supports data flow between nearest neighbor cells. Control signals can be distributed over longer distances using bus-like connections. ASTRAs (logic and interconnect) silicon area is shown to be quite low while still providing sufficient flexibility for real-life applications. First benchmarking results with traditional applications from DSP domain show that ASTRA is competitive with respect to ASIC in terms of silicon area and power consumption

High Throughput and Low Power Reed Solomon Decoder for Ultra Wide Band

Reed Solomon (RS) codes are widely used in a variety of communication sys- tems. Continual demand for ever higher data rates makes it necessary to devise very high-speed implementations of RS decoders. In this chapter, a uniform comparison is drawn for various algorithms and architectures proposed in the literature, which help in selecting the appropriate architecture for the intended application. Dual-line architecture of modified Berlekamp Massey algorithm is chosen for Ultra Wide Band (UWB). Using 0.12 µm technology the area of the design is 0.22 mm 2 and throughput is 1.6 Gbps. The design dissipates only 14 mW of power in the worst case, including memory, when operating at 1.0 Gbps data rate.

Towards a guided design flow for heterogeneous reconfigurable architectures

In this work we present a concept of an architecture design flow for heterogeneous reconfigurable architectures. We have a special focus on high flexibility regarding the architecture design. We cover architectures from fine-grained island-style FPGAs and heterogeneous hierarchical structures through to coarse-grained reconfigurable architectures (CGRAs). Our goal is to make the development and optimization of reconfigurable architectures more efficient and convenient. Therefore our design flow includes a graphical architecture editor, which allows the user to adapt the global design structure as well as the detailed implementation of the logic blocks. An analysis tool gives the user a statistical feedback about the resource utilization of the architecture under development for a given set of benchmark applications to allow a directed exploration and optimization. We describe the envisioned design flow and compare it to a manual design flow. Finally we present the parts of the toolset that are already operational and describe how we are planning to implement the remaining tools.

Architecture Template and Design Flow to Support Application Parallelism on Reconfigurable Platforms

This paper introduces the ReSArT ( Reconfigurable Scalable Architecture Template). Based on a suitable design space model, ReSArT is parametrizable, scalable, and able to support all levels of parallelism. To derive architecture instances from the template, a design environment called DEfInE ( Design Environment for ReSArT Instance G eneration) is used, which integrates some existing academic and industrial tools with ReSArT-specific components, developed as a part of this work. Different architecture instances were tested with a set of 10 benchmark applications as a proof of concept, achieving a maximum degree of parallelism of 30 and an average degree of parallelism of nearly 20 16-bit operations per cycle.