Martin Brox

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext.

A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques

A 512Mb DRAM operates up to a data-rate of 2Gb/s/pin. It employs an averaging pad-driver design which reduces simultaneous switching noise to one third of a conventional design. Resistive damping elements eliminate the level degradation of the receivers caused by an oscillation of the on-chip ground. A technique for cancelling line-to-line coupling noise is also described

DRAM and eRAM

Demand growth for electronic systems has been driven by new consumer and computing applications. The most popular examples are the next-generation, high-resolution game-consoles. These systems heavily leverage the performance of today’s memories and processors. Yet, these applications are still unable to create a life-like experience due to the limitations of the onand off-chip memory bandwidth available to the processing functions. Careful optimization of the memory hierarchy bandwidth is necessary to improve system performance. High-speed embedded-DRAM (eDRAM) has evolved as a serious contender to embedded-SRAM (eSRAM), while external datarates continue their rapid rise. However, speed improvements cannot stand on their own as system costs must be kept reasonable. To this end, good test and repair solutions reduce cost and facilitate higher levels of integration. The presentations in this session report recent advances that address these challenges.

Session 11 Overview: DRAM

A growing number of mobile and consumer applications drive DRAM development toward divergent targets. Low power is needed for long battery life, while high speed is needed for graphics and embedded applications. In the first group of presentations various embedded DRAM macros demonstrate gains in performance and supply voltage. The rest of the session focuses on improving the I/O-interface of the memories, a problem of continuously increasing importance in todays bandwidth-hungry applications. Paper 11.1 describes a 16Mb embedded DRAM macro using a 90nm 6-Metal embedded DRAM process. It has a DRAM core voltage of only 0.6V enabled by a positive and negative body bias regulation. Even at 0.6V, the power-efficient mid-level bitline sensing can be demonstrated with a trench cell of 40fF. A 205MHz operation is achieved with 19.5nsec access (tRC) and 39mW operating power. Another approach for low standby power with high speed for embedded DRAM macro is proposed in Paper 11.2. Power Down Data Retention (PDDR) and Self-adjustable Timing Control (STC) are featured. A 312MHz tRC, 16Mb DRAM macro is realized using a 0.13µm TaO CUB cell and low-power process.