Wolfgang Spirkl

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext.

Fully automated semiconductor operating condition testing

In this article we present a test flow for fully automated operating condition testing (AOCT) for semiconductor devices. The test flow consists of three major modules to provide maximum test coverage, automated identification of fault related operating conditions and localization of the range of these conditions, i.e. the pass-to-fail transitions with high resolution. For maximum coverage when testing for many independent timing and level conditions at the same time we use a Monte Carlo approach as the first step of the flow. In the second module fault related operating conditions are identified by analyzing the distribution of failure conditions through a novel statistical approach. The third module of the flow localizes the multidimensional pass-to-fail transitions. We present two algorithmic options, not previously applied for operating condition testing, one based on a Genetic Algorithm search and the second one based on the recursive divide-and-conquer principle. We finally present an application example of the flow to memory devices. The test flow can be implemented on all ATEs supporting a programming or scripting language for control of the tester

A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques

A 512Mb DRAM operates up to a data-rate of 2Gb/s/pin. It employs an averaging pad-driver design which reduces simultaneous switching noise to one third of a conventional design. Resistive damping elements eliminate the level degradation of the receivers caused by an oscillation of the on-chip ground. A technique for cancelling line-to-line coupling noise is also described

Optimal Finite-Time Endoreversible Processes—General Theory and Applications

Abstract We treat the general problem of transferring a system from a given initial state to a given final state in a given finite time such that the produced entropy or the loss of availability is minimized. This problem leads to a second-order differential equation similar to the Euler–Lagrange equation. However, while mechanical systems naturally follow the trajectory that minimizes the action, a thermodynamic system does not tend to minimize dissipation, rather an external control is required, for which we give the equations. We give exact equations for the optimal process for the general case of a nonlinear system with several state variables, and show solved examples for the case of two state variables. Not only the speed but also the path depends on the available time. For linear processes, e.g. in the limit of slow processes or if the Onsager coefficients do not depend on the fluxes, we find a constant entropy-production rate or a constant loss rate of availability and an optimal path independent of the available time .