Hon-Sum Wong

CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFETs, low-temperature CMOS, and double-gate MOSFETs, which may lead to the outermost limits of silicon scaling.

Beyond the conventional transistor

This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

Design and performance considerations for sub-0.1 /spl mu/m double-gate SOI MOSFET'S

We present a simulation-based analysis of the device design and circuit performance trade-offs between short channel immunity and parasitic device capacitances of sub-0.1 /spl mu/m double-gate SOI MOSFETs. We demonstrate that perfect alignment of the bottom gate to the top gate is not necessary to achieve adequate short channel immunity but is required to maintain short gate delays. Double-gate MOSFET device design guidelines are provided.<<ETX>>

Experimental verification of the mechanism of hot-carrier-induced photon emission in n-MOSFET's with a CCD gate structure

New experimental data are presented to verify the physical mechanism of hot-carrier-induced photon emission in n-MOSFETs. The multiple gates are biased to create hot electron populations either at the drain junction or at the interelectrode gap regions by using MOSFETs with an overlapping CCD (charge coupled device). Results show that the magnitudes of the photon-generated minority carrier collected were comparable for hot-carrier-induced photons emitted from the drain junction and from the interelectrode gap regions, although the density of charged centers available for Bremsstrahlung for both situations differed by about two orders of magnitude. These results show unambiguously that Bremsstrahlung of hot electrons in the Coulomb field of ionized drain dopants is not the sole mechanism responsible for hot-carrier-induced photon emission in n-MOSFETs.<<ETX>>

Fabrication of ultrathin, highly uniform thin-film SOI MOSFETs with low series resistance using pattern-constrained epitaxy

We report a novel fabrication process for self-aligned, ultrathin, highly uniform thin-film SOI MOSFETs with low series resistance. Self-aligned, ultrathin SOI n-MOSFETs with 8 nm-50 nm undoped channel were fabricated. For n-MOSFETs with a 0.2 /spl mu/m effective channel length, a saturation transconductance of 242 mS/mm, and a low series resistance (R/sub s/d/=333 /spl Omega//spl middot//spl mu/m) were obtained.

“Universal” effective mobility of empirical local mobility models for n- and p-channel silicon MOSFETs

Abstract Several experimental investigations have shown that the measured effective mobility falls on one common curve (the Universal Mobility Curve) independent of the substrate doping density and the source-to-substrate bias if the effective mobility is plotted vs the effective field. This paper reports on the relationship between the effective field (a non-local electric field mobility model) and the local mobility models employed in drift-diffusion device simulators. Using a drift-diffusion device simulator which implements several mobility models in the same simulator, we show that not all local mobility models agree with the empirical universal mobility behavior for both n -channel and p -channel MOSFETs when the simulated results are interpreted as “experimental” data. Furthermore, some local mobility models do not agree with the universal mobility behavior if the device has compensated channel doping (such as a typical CMOS p -channel device).

Experimental verification of the mechanism of hot-carrier-induced photon emission in n-MOSFETs using an overlapping CCD gate structure

Experimental data are presented to verify the physical mechanism of hot-carrier-induced photon emission in n-MOSFETs. Using MOSFETs with an overlapping CCD gate structure, the multiple gates are biased to create hot-electron populations either at the drain junction or at the interelectrode gap regions. The results show that the magnitudes of the photon-generated minority carriers collected were comparable for hot-carrier-induced photons emitted from the drain junction and from the interelectrode gap regions, although the density of oppositely charged Coulomb centers (i.e. ionized drain dopants) available for bremsstrahlung in the interelectrode gap region is zero. These results show unambiguously that, for above-bandgap low-energy photons, bremsstrahlung of hot electrons in the Coulomb field of oppositely charged centers is not the dominant mechanism responsible for hot-carrier-induced photon emission in n-MOSFETs.<<ETX>>

Gate-current injection and surface impact ionization in MOSFET's with a gate induced virtual drain

In this paper, gate current injection into the gate oxide of MOSFETs with a split-gate (virtual drain) structure is examined. The split-gate structure is commonly employed in flash EEPROM and CCDs. An important parameter characterizing the gate current injection is the ratio phi /sub b// phi /sub i/ (where phi /sub b/ is the effective energy barrier for electron injection into gate oxide, and phi /sub i/ is the impact ionization energy). We present new experimental data of the ratio phi /sub b// phi /sub i/ measured at relatively constant vertical and lateral electric fields. Using a novel triple-gate MOSFET, the vertical field, the lateral field, and the drain current of the MOSFET can be independently controlled using proper biases. The measured phi /sub b// phi /sub i/ ranged from 2.6 to 3.2 depending on gate and drain biases, and gate geometry.<<ETX>>

Gate current injection in MOSFET's with a split-gate (virtual drain) structure

Gate current injection into the gate oxide of MOSFETs with a split-gate (virtual drain) structure is examined. The split-gate structure is commonly encountered in flash EEPROM and CCDs. An important parameter characterizing the gate current injection is the ratio phi /sub b// phi /sub i/ (where phi /sub b/ is the effective energy barrier for electron injection into gate oxide, and phi /sub i/, is the impact ionization energy). Measurements of phi /sub b// phi /sub i/ at relatively constant vertical and lateral electric fields are reported. Through the use of a novel triple-gate MOSFET, the drain current as well as the lateral and vertical electric field at the point of injection were independently controlled during the measurements. The measured phi /sub b// phi /sub i/ showed a dependence on gate and drain biases not reported previously.<<ETX>>