Mary Claire Silvestre

Bevel rinse optimization for reduced edge defectivity and improved edge yield

As a technology ramps up to volume manufacturing, it becomes imperative that variability in yield is reduced. One of the leading contributors to this variation is coming from the wafer edge where uniformity in film thickness significantly rolls-off. In order to widen the process margin at the edge, most advance technologies will remove the edge bead removal in lithography steps to extend the area that remains within the depth of focus. However, without the edge bead removal some photochemical residue was observed at the wafer edge and bevel. A partition inspection on the wafer bevel showed that the photoresist stack at the bevel area is not completely removed. With the process of record rinse at the lithography step, a thicker layer of patterning material is left at the bevel which downstream bevel clean processes cannot remove. By optimizing the bevel rinse, removal of the remaining organic films was improved. The film cut from the patterning layers are receded away from the bevel by tuning the wafer rotation speed during rinse and optimizing the rinse duration. With the optimized rinse it was shown that defect count at the bevel as well as the center to edge yield ratio is improved.

Hammer test to detect BEOL process marginalities on via chains in advanced nodes

In advanced nodes of 28nm and below, inline detection of a process issue inline is very challenging. Inline detection of process marginalities through Characterization Vehicle® (CV®), scribe line structures and optical scans are becoming more challenging. With the technology shrink and complex designs, the Characterization Vehicle® (CV®) and scribe line structures cannot completely represent the product designs. The optical scans were also less effective compared to past nodes due to the signal-noise ratio. Also the optical scans are effective to detect an issue that happens on the surface of the silicon rather than something buried. This paper discusses a methodology that was able to detect successfully the issue inline saving a lot of time in a manufacturing environment.

Vertical natural capacitor time dependent dielectric breakdown (TDDB) improvement in 28nm

Ultra Low-K films are used in advanced technologies as an interlayer dielectric in Cu processing. Due to its high porosity, it poses a lot of process challenges. This paper discusses one challenge it posed for reliability of vertical natural capacitors (VNCAP). When a new Cu-CMP slurry was evaluated for its improved performance for defects and uniformity, degradation of the time dependent dielectric breakdown (TDDB) lifetime for VNCAP was observed. Studies have been performed to characterize the interaction of the deposited film to the CMP process. In the course of this investigation, it was observed that the post-CMP clean chemistry impacts the TDDB lifetime. By characterizing the ULK surface post-CMP, and establishing inline correlations to TDDB lifetime, a new process was identified quickly to improve the TDDB lifetime by 2 orders.

Effect of top corner rounding in BEOL to yield in advanced technologies

In advanced technologies as the dimensions shrink, even the slight change in profiles can cause issues in BEOL integration. This paper discusses the effect of dielectric profile on product yield. Even though these issues were not seen on standard monitoring structures, the issue has been observed in products of very complicated design structures. The yield losses for this failure mechanism range from 10% to 20%. The fails being more of a functional fail than a physical failure made the problem even more complicated. Here we discuss how the issue was identified by data mining, followed by in depth investigation on individual module and understanding the interactions. By understanding the interaction between process modules, an optimized and manufacturable solution was derived and implemented. The issue was addressed by optimizing the film treatment and the wet-clean optimization, as an integrated module approach. Yield was verified on this optimized process and proven.

Nested interconnect macro electrical yield improvement for advanced triple patterning integration

For metal pitches below 50nm, triple patterning (LELELE) integration is utilized in most advanced technologies to build the Cu interconnect. This integration relies on etch to shrink to the target critical dimension. As a result of high iso-dense bias in conventional etch process, nested serpentine structures formed by different metal colors show massive shorts that limit defect density yield. In this paper, several approaches in improving the iso-dense bias, as well as improving the nested serpentine electrical yield will be discussed.

Optimizing Cu barrier thickness for interconnects performance, reliability and yield

Cu barrier thickness optimization on our 90nm pitch Vx/Mx layers with porous ULK SiCOH (κ=2.55) was systematically investigated. Both via resistance and intrinsic EM performance favors thinner TaN and Ta films, however, the robustness of the plating requires thicker Ta to improve seed quality that withstand dissolution during plating. Overall, a thin TaN barrier with moderate thick Ta provides the optimum solution for performance, reliability and yield.

10nm local interconnect challenge with iso-dense loading and improvement with ALD spacer process

10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates the limited process margin resulting from iso-dense loading during dry etch CD shrink, and proposes a novel ALD spacer-shrink process which improves iso-dense CD difference by 50%.

Trench first metal hardmask post-lithography novel rework process for defectivity and yield improvement

A conventional back end of line (BEOL) post-lithography rework process is usually considered as a non-critical process compared to other process steps in a silicon flow in advanced technologies. This paper discusses the impact of this non-critical process to defectivity and yield. For advanced technology nodes using a tri-layer trench first lithography stack, the conventional rework process was proven to be inefficient. The trench first metal hardmask post-lithography conventional rework process resulted in a massive organic residues from the anti-reflective coating material used. Detailed studies were performed to isolate the source of the defects. Novel dry rework process showed improved performance compared to the conventional wet clean process that has been traditionally used. This novel process has proven to improve yield, manufacturing cycle time and cost.

An investigation of process dependence of porous IMD TDDB

Process sensitivity of IMD TDDB in a vertical natural capacitor (VNCAP) structure was evaluated in this paper. Among others, CMP slurry and wet clean chemical were found to have higher level of interaction impacting TDDB performance. This enables proper process optimizations, such as reduction in the Cu+ concentration on ULK top surface. Additionally, dependence of the structure was analyzed and the top metal layer is identified as the weakest link in VNCAP failure. A solution for this was described and it involves accelerated thermal cure step which successfully recovered dielectric electric strength.