Anbu Selvam Km Mahalingam

Metal wiring critical dimension shrink using ALD spacer in BEOL sub-50nm pitch

In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple patterning (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. In this paper, we demonstrate metal critical dimension (CD) shrinkage using atomic layer deposition (ALD) enabled spacer layer to achieve sub-50 nm pitch. ALD spacer thickness is identified as the crucial parameter to achieve target CD. An optimization study correlating oxide thickness, final CD and electrical yield is presented. An optimized recipe that results in 50% shrinkage is identified with good electrical yield.

Hammer test to detect BEOL process marginalities on via chains in advanced nodes

In advanced nodes of 28nm and below, inline detection of a process issue inline is very challenging. Inline detection of process marginalities through Characterization Vehicle® (CV®), scribe line structures and optical scans are becoming more challenging. With the technology shrink and complex designs, the Characterization Vehicle® (CV®) and scribe line structures cannot completely represent the product designs. The optical scans were also less effective compared to past nodes due to the signal-noise ratio. Also the optical scans are effective to detect an issue that happens on the surface of the silicon rather than something buried. This paper discusses a methodology that was able to detect successfully the issue inline saving a lot of time in a manufacturing environment.

Cu seed optimization for minimum pitch wiring in 10nm and beyond

Technology scaling necessitates interconnect structures (metal and vias) in the back end of the line (BEOL) module to sub 50nm pitch. This presents significant challenges to the conventional metallization scheme, consisting of liner, seed deposition and Cu plating. Seed layer deposition particularly is quite challenged because of increasing aspect ratio. Additionally, the presence of hard mask in the local metal interconnects (Mx) induces undercut in the metal line profile making metallization even more challenging. The consequence is a significant increase in metal voiding defects as compared to previous technology nodes. Hence the conventional metallization scheme requires reengineering to suit the needs of advanced nodes. In this paper, a systematic approach to tune and optimize the copper seed deposition and its effect on metal electrical yield is presented. Through design of experiments (DOE) the metal open yield (post high temperature anneal-hammer test) improved from less than 10% to greater than 50% for the optimized seed deposition recipe (post stress). The optimized recipe reduced the void related defects responsible for the lower metal open yield. Results from current ramp test, via chain yield and electromigration data will be presented for the optimized seed recipe.

Effect of top corner rounding in BEOL to yield in advanced technologies

In advanced technologies as the dimensions shrink, even the slight change in profiles can cause issues in BEOL integration. This paper discusses the effect of dielectric profile on product yield. Even though these issues were not seen on standard monitoring structures, the issue has been observed in products of very complicated design structures. The yield losses for this failure mechanism range from 10% to 20%. The fails being more of a functional fail than a physical failure made the problem even more complicated. Here we discuss how the issue was identified by data mining, followed by in depth investigation on individual module and understanding the interactions. By understanding the interaction between process modules, an optimized and manufacturable solution was derived and implemented. The issue was addressed by optimizing the film treatment and the wet-clean optimization, as an integrated module approach. Yield was verified on this optimized process and proven.

Nested interconnect macro electrical yield improvement for advanced triple patterning integration

For metal pitches below 50nm, triple patterning (LELELE) integration is utilized in most advanced technologies to build the Cu interconnect. This integration relies on etch to shrink to the target critical dimension. As a result of high iso-dense bias in conventional etch process, nested serpentine structures formed by different metal colors show massive shorts that limit defect density yield. In this paper, several approaches in improving the iso-dense bias, as well as improving the nested serpentine electrical yield will be discussed.

Optimizing Cu barrier thickness for interconnects performance, reliability and yield

Cu barrier thickness optimization on our 90nm pitch Vx/Mx layers with porous ULK SiCOH (κ=2.55) was systematically investigated. Both via resistance and intrinsic EM performance favors thinner TaN and Ta films, however, the robustness of the plating requires thicker Ta to improve seed quality that withstand dissolution during plating. Overall, a thin TaN barrier with moderate thick Ta provides the optimum solution for performance, reliability and yield.

10nm local interconnect challenge with iso-dense loading and improvement with ALD spacer process

10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates the limited process margin resulting from iso-dense loading during dry etch CD shrink, and proposes a novel ALD spacer-shrink process which improves iso-dense CD difference by 50%.

Optimization of wet clean and its impact on sub-50 nm pitch BEOL yield

In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple pattering (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. This scenario has imposed increased demands on many of the semiconductor processes involved in the fabrication of integrated circuits. One such process is the wet clean process. In this paper, a direct correlation between clean chemistry and metal/via electrical yield is shown in M1 module of 10 nm technology node. Line and via open yield improved 10X upon adding iso propyl alcohol (IPA) to the standard dilute hydrofluoric acid (dHF) aqueous solution. IPA acts as an inhibitor, and reduces the surface tension, thus preventing over-aggressive etch and displacement of pattern structures during the clean process.

Trench first metal hardmask post-lithography novel rework process for defectivity and yield improvement

A conventional back end of line (BEOL) post-lithography rework process is usually considered as a non-critical process compared to other process steps in a silicon flow in advanced technologies. This paper discusses the impact of this non-critical process to defectivity and yield. For advanced technology nodes using a tri-layer trench first lithography stack, the conventional rework process was proven to be inefficient. The trench first metal hardmask post-lithography conventional rework process resulted in a massive organic residues from the anti-reflective coating material used. Detailed studies were performed to isolate the source of the defects. Novel dry rework process showed improved performance compared to the conventional wet clean process that has been traditionally used. This novel process has proven to improve yield, manufacturing cycle time and cost.