Mary Yvonne Lanzerotti

Design of the Power6 Microprocessor

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models

Computer hardware components have changed significantly since the 1960s, 1970s, 1980s, and even since the early 1990s. Work concerning Rents memos prior to the present paper has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent while working at IBM, even though todays computer components are significantly different from those in 1960 and 1971. However, because of the significant changes in the design and implementation of computer hardware components since 1960 and 1971, a new interpretation of Rents memos is needed for todays components. We have obtained copies of Rents two memos. In these memos, Rent describes the method that he used to obtain an empirical relationship between properties of the computer hardware components of the IBM 1401 and the IBM 1410 computers. We have studied these memos carefully in order to understand Rents original intent. Based on our careful reading of these two memos, the personal knowledge of one of us with the 1401 and 1410 computers, and our experience designing ultralarge-scale integrated (ULSI) circuits for high-performance microprocessors, we have derived an historically equivalent interpretation of Rents memos suitable for todays computer components. The purpose of this paper is to present a new interpretation of the memos and to present an application to wirelength distributions of real ULSI circuitry. In this paper, we will: 1) describe the contents of the memos and Rents method; 2) provide an historically-equivalent interpretation of Rents memos for todays computer components; and 3) apply this new interpretation to real ULSI control logic circuitry in the 1.3-GHz IBM POWER4 microprocessor. In this paper, we will show that this new interpretation of the two memos provides improved wirelength distribution models with better qualitative agreement with measurements and more accurate estimates of wirelength distributions and wirelength requirements for real ULSI designs compared with prior methods.

Modeling and Forecasting of Defect-Limited Yield in Semiconductor Manufacturing

A detailed cause-and-effect stochastic model is developed to relate the type, size, location, and frequency of observed defects to the final yield in IC manufacturing. The model is estimated on real data sets with a large portion of unclassified defects and un inspected layers, and in presence of clustering of defects. Results of this analysis are used for evaluating kill ratios and effects of different factors, identifying the most dangerous cases and the most probable causes of failures, forecasting the yield, and designing optimal yield-enhancement strategies.

Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry

This paper presents a comprehensive assessment of interconnect requirements in ULSI control logic circuitry and quantifies the agreement observed (1) between estimates and measurements of average wire-length in individual designs in real chips, and (2) between wire-length distributions provided by the models and wire-length distributions obtained from measurements. In this study, actual interconnect data is measured in ASIC-like control logic designs in the six functional units of the 1.3GHz POWER4. This paper compares interconnect measurements with estimates for control logic in individual designs, in functional units, and in the entire POWER4 core. The results presented in this paper show that the estimates are typically lower than the actual wire-length measurements. The results also show that the estimates of the total wire-length for all of the control logic in the POWER4 agree to within 31% of the total measured wire-length.

Assessment of on-chip wire-length distribution models

Ultralarge-scale integrated (ULSI) chip design data is needed for an assessment of existing on-chip wirelength distribution models. Data extracted from modern chips such as high-performance microprocessors provide information about actual wire length requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by evaluating existing models as functions of Rents parameters that are extracted from the designs. This brief assesses the extent to which existing models estimate wirelength requirements in 100 ASIC-like control logic designs in the 1.3-GHz POWER4 microprocessor. For each design, physical design characteristics and wirelength requirements are measured and compared with model estimates. Lack of agreement between the data and models is observed for most designs, and possible reasons for the lack of agreement are discussed.

Impact of interconnect length changes on effective materials properties (dielectric constant)

This paper presents models and a methodology to evaluate tradeoffs between technology and design to obtain the highest frequency in ULSI design projects and quantifies the performance improvement that can be expected. With respect to the standard chip design process, it is well known in the academic community that circuits and chips are required to satisfy specific constraints, most notably the requirement that all signals must have zero slack when the transistors and wires are manufactured at some pre-specified technology node. To amortize the cost of the design process, which is time-consuming and complex, there is a need to migrate the designs to future technology nodes with minimal redesign. However, this problem and the associated implications of design migration are less well known, and at present there are no existing models to help designers evaluate whether migrated designs will operate successfully in a future technology or whether migrated designs will fail and thus cause chip failure. Thus, there is a need for research to evaluate the impact of design changes on chip performance. This paper presents a methodology to evaluate and quantify the performance impact of design changes, where we express the impact on performance as an effective change in dielectic constant in the wire environment. In this study, as in a previous study[1], performance estimates obtained from the model are compared with values obtained for interconnections in 18 ASIC-like control logic designs in the Instruction Fetch Unit (IFU) of the 1.3GHz POWER4 microprocessor.

Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution

Power reduction techniques are a critical issue in the design of todays ULSI chips. This paper is concerned with methods to characterize the capacitive load on the POWER4 on-chip global clock distribution [1], which is a large contributor to the overall chip power dissipation. A characterization of the capacitive load is needed because the contributions of the on-chip devices and interconnections are typically overestimated and are not well understood for high performance microprocessors. One problem that results from the lack of this information is excessively high power dissipation in the chip global clock distribution; the global clock distribution is over-designed and stronger than necessary to drive the actual (lower) chip load. Information about the capacitive load is difficult to obtain because the data volume is large, and extracting the interconnect data is a complex task. Sophisticated computer software is needed to extract the circuit and physical design data for hundreds of devices and wire segments within the chip design schedule.This paper presents the first comprehensive characterization of the clock load for ASIC-like control logic designs in the 1.3GHz POWER4 microprocessor core [1], [2]. This characterization was achieved with the use of sophisticated software written for this study to accomplish the task of extracting the data from these designs. Analysis of the data shows that the wire contribution to the chip capacitive load is significant and can increase the capacitive load of a design by 30% on average and by as much as 130% for some designs. The results also suggest that the wire load contribution on each metal layer can be reduced if an alternate interconnect design style is selected. Two alternate design styles are presented and show that a capacitive load reduction of 8.4% to 20% is expected for each design. Extended to the entire chip, the results show that the load reduction for the core is expected to be as high as 10%. These values are large enough that one alternate design style has been implemented in the design methodology of future chips.