Thomas J. Bucelot

Indium channel implant for improved short-channel behavior of submicrometer NMOSFETs

Indium has been used as an alternative channel implant in submicrometer-channel Si MOSFETs in order to obtain highly nonuniform channel doping. Superior device characteristics have been obtained down to 0.17- mu m channel length. The device characteristics have been compared to those of uniform boron-implanted short-channel MOSFETs used in a 0.25- mu m CMOS technology. Results indicate that NMOSFETs with nonuniform channel doping obtained with indium have superior short-channel effect (SCE) when compared to NMOSFETs with uniformly (boron) doped channel.<<ETX>>

A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor

Resonant clock distributions have the potential to save power by recycling energy from cycle-to-cycle while at the same time improving performance by reducing the clock distribution latency and filtering out non-periodic noise. While these features have been successfully demonstrated in several small-scale experiments, there remained a number of concerns about whether these techniques would scale to a product application. By modifying the Cell broadband engine processor to incorporate a large resonant global clock network, power savings with full functionality is demonstrated over a 20% range in clock frequencies, and a 6-8 Watt power savings at 4 GHz. This was achieved by changing one wiring level and adding an additional thick copper level to create inductors and capacitors.

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.

A highly latchup-immune 1-&#181;m CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi 2

A 1-µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. Important features in this technology include thin epi substrate, retrograde n-well formed by 1-MeV ion implantation, As-P graded junctions, and self-aligned titanium disilicide. The 1-µm CMOS technology has been characterized by examining the deviceI-Vcurves, avalanche-breakdown voltages, subthreshold characteristics, short-channel effect, and sheet resistances. The devices fabricated by using the 1-MeV ion implantation and self-aligned titanium disilicide do not deviate from the conventional devices constructed with the same level of technology. With the As-P double-diffused LDD structure for the n-channel device, the avalanche-breakdown voltage is increased and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain and the polysilicon gate to 3 Ω/□ compared with 150 Ω/□ of the unsilicided counterparts. The optimized 1-µm device channel n-well CMOS resulted in a propagation delay time of 150 ps with a power dissipation of 0.3 mW. With the thin epi wafers and the retrograde n-well structure, latchup immunity is found to be greatly improved. Moreover, with the titanium disilicide formation on the source-drain, the latchup holding voltage is found to be extremely high (13 V) with the substrate grounded from the backside of the wafer. If the backside substrate is not grounded, self-aligned disilicide over n+and p+regions are found necessary to ensure high latchup immunity even in the case of thin epi on heavily doped substrate. The degradation of emitter efficiency due to the TiSi2is believed to be the dominant factor in raising the holding voltage. Detailed experimental results and discussions are presented.

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor

Resonant clocking techniques show promise in reducing global clock power and timing uncertainty (skew and jitter). By resonating the large global clock capacitance with an inductance, the energy used to charge the clock node each period can be recycled within the LC tank network, resulting in lower clock power. Additional power savings are realized by reducing the strength of clock drivers because only losses need to be overcome at resonance. Skew and jitter are improved due to the bandpass characteristic of the LC network and the use of fewer clock buffering stages. We describe how the Cell Broadband Engine (Cell BE) processor is experimentally transformed to have a resonant-load global clock distribution similar to the one in (Chan et al., 2004).

Analysis of silicide process defects by non-contact electron-beam charging

Electron beam charging without any conventional electrical measurements has been used to understand gate electrode leakage currents in a silicide process. Using this technique, it was determined that the leakage is caused by single defects which are small compared to the typical circuit dimensions, which occur on the gate perimeter, and are randomly distributed. Combined with one additional process step, it was determined that the leakage is not due to silicide bridging, but rather to a gate oxide overetch. The measurement has been instituted as an inline process monitor to screen for silicide leakage defects.<<ETX>>

A 4 Mb Low-temperature DRAM

The authors present the characterization of the first dynamic RAM (DRAM) fabricated in a technology specifically optimized for cryogenic operation. With the power supply adjusted to assure hot-electron reliability, the 25-ns 4-Mb low-temperature (LT) chips operated 3 times faster than conventional chips. The LT-optimized chips functioned properly with cycle times as fast as 45 ns, and with a toggle-mode data rate of 667 Mb/s. Wide operating margins and a very large process window for data retention were demonstrated. At a temperature of 85 K the storage retention time of the trench-capacitor memory cells exceeded 8 h. This study shows that the performance leverage offered by low temperature applies equally well to DRAM and to logic. There is no limitation inherent to memory. >

Infrastructure requirements for a large-scale, multi-site VLSI development project

This paper describes the design infrastructure and environment that were established to support the multi-site design of the IBM POWER4 microprocessor. The Common Tools Environment was created to provide a consistent means for accessing design tools and initiating operating system variables from multiple sites in a site-independent manner. The AIX® operating system and the Common Tools Environment masked local, site-specific details of the design environment, allowing site-specific design practices, shared storage, and information system policies to be transparently maintained. The design datamanagement system, the importance of highly reliable wide- and local-area networks, and the establishment of automated network monitoring are discussed.

Resonant clock mega-mesh for the IBM z13 TM

The IBM z13TM microprocessor utilizes a large resonant “mega-mesh” global clock distribution saving 50% of the final-stage clock mesh power and 8% of the total chip power in the desired frequency range of 4.5 to 5.5 GHz compared to a simulated, non-resonant base-line design. The mega-mesh is driven by pulsed buffers. Measurement of the mega-meshs robustness is enabled by skew gradients created by programmable delays. The design is implemented in IBMs high-performance 22nm high-k CMOS SOI technology with 17 metal layers [1].

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8 TM microprocessor

A resonant-clock design for the IBM POWER8 processor core was implemented with 2 resonant modes (and a non-resonant mode), saving clock power over a wide frequency range from 2.5GHz to more than 5GHz. The POWER8 microprocessor is composed of 12 chiplets, each containing a single resonant clock grid for one core and its L2 cache, and a half-frequency, non-resonant clock grid for the L3 cache. The clock grids drive the local clock buffers (LCBs) that in turn drive the latches. The LCBs are gated off to measure the global clock power from the PLL to the LCBs. The resonant core communicates synchronously with the L3, requiring low skew between the domains. The chip was designed in a 22nm SOI process, including two ultra-thick-metal (UTM) layers (3 microns thick) for power distribution, I/O, all long global clock wires, and the resonant clock inductors. The UTM technology reduces wire resistance and simplifies inductor design, but requires accurate transmission line modeling and special routing.