Maryam Ashouei

Checksum-Based Probabilistic Transient-Error Compensation for Linear Digital Systems

In this paper, a probabilistic compensation technique for minimizing the effect of transient errors effect is proposed. The focus is to develop a compensation technique for DSP applications in which exact error compensation is not necessary and end-to-end system level performance is degraded minimally as long as the impact of the ldquonoiserdquo injected into the system by the transient errors is minimized. The proposed technique, called checksum-based probabilistic compensation, uses real-number checksum codes for error detection and partial compensation. Traditional coding techniques need a code of distance three and relatively complex calculations for perfect error correction. Here, it is shown that a distance-two code can be used to perform probabilistic error compensation in linear systems with the objective of improving the signal-to-noise ratio in the presence of random transient errors. The goal is to have a technique with small power and area overhead and to perform compensation in real time with negligible latency. The proposed technique is comprehensive and can handle errors in the combinational circuitry and storage elements. Comparison against a system with no error correction shows that up to 13-dB SNR improvement is possible. The area, power, and timing overheads of the proposed technique are analyzed.

Statistical estimation of correlated leakage power variation and its application to leakage-aware design

Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. It has been shown that the layout of a circuit can significantly affect the variation in leakage power by controlling the effect of spatially correlated across-die process variations. In this paper, a method, which efficiently estimates the distribution of leakage power variation caused by correlated process variations, is proposed. The accuracy of the method was validated by comparing the estimated leakage power distribution with Monte Carlo simulation results on ISCAS benchmark circuits. Furthermore, it is shown how the method can be used as a guideline to determine the best possible layout of a circuit.

Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors

It is well known that scaled CMOS technologies are increasingly susceptible to induced soft errors and environmental noise. Probabilistic checksum-based error detection and compensation has been proposed in the past for scaled DSP circuits for which a certain level of inaccuracy can be tolerated as long as system-level quality-of-service (QoS) metrics are satisfied. Although the technique has been shown to be effective in improving the SNR of digital filters, it can only handle errors that occur in the system states. However, the transient-error rate of combinational logic is increasing with technology scaling. Therefore, handling errors in the arithmetic logic circuitry of DSP systems is also essential. This is a significantly more difficult task due to the fact that a single error at the output of an adder or multiplier can propagate to more than one system state causing multiple states to be erroneous. In this paper, a unified scheme that can address probabilistic compensation for errors both in the system states and in the embedded adders and multipliers of DSP filters is developed. It is shown that by careful checksum code design, significant SNR improvements (up to 13 dB) can be obtained for linear filters in the presence of soft errors.

Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums

Soft errors due to alpha particles, neutrons and environmental noise are of serious concern in highly scaled CMOS circuits. This mandates the use of error/noise tolerance mechanisms in circuit design. Prior work has addressed error correction and compensation techniques for linear digital systems using checksum codes. However no low-cost checksum based technique is found in the literature for nonlinear digital signal processing systems. The problem of error detection and compensation in nonlinear systems is harder due to difficulties in encoding nonlinear operations and correcting for errors in the same. This paper presents a checksum based technique for error compensation in nonlinear digital filters using the time-freeze linearization method. The technique uses distance-two linearized checksum error detection codes for SNR improvement using probabilistic error compensation instead of deterministic error removal. It is shown that by careful checksum code design, significant filter SNR improvement can be obtained in the presence of soft errors.

Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations

As technology scales to 40nm and beyond, intra-die process variability causes large delay and leakage variations across a chip in addition to expected die-to-die variations. In this paper, a new approach to post-manufacture circuit adaptation for yield maximization is proposed with special focus on the projected large intra-die variability of future CMOS technologies. Adaptation is achieved through an iterative implicit delay test (IDT) and reconfiguration procedure. The IDT is used to assess the timing of the circuit every time it is reconfigured until the best (with the lowest leakage) configuration, achievable within a specified reconfiguration time, is obtained. Since accurate delay testing is not possible at each step of the reconfiguration process, statistical correlation-based methods are used to determine the circuit timing. Reconfiguration is achieved by activating programmable gates that can be switched from a low-speed/low-leakage mode to a high-speed/high-leakage mode under digital control. The circuitry for self-adaptation is very simple, no external tester support is necessary and results show that a significant yield improvement is possible

Test volume reduction via flip-flop compatibility analysis for balanced parallel scan

Test generation for scan-based test of sequential circuits is typically performed by generating tests for the embedded combinational logic (ECL) and translating these into scan test vectors. However, the serial nature of scan-based test incurs significant overhead in terms of test application time. To reduce the test data volume, in this paper we propose a new algorithm for compatibility analysis of the circuit flip flops. This algorithm, when applied to parallel-scan methods such as the Illinois Scan Architecture (ILS), results in shorter and more balanced scan chains. It also eliminates the need to apply test vectors in serial mode. As a result, an average reduction of 1.4/spl times/ and a maximum reduction of 1.7/spl times/ in test data volume was obtained for the ISCAS89 benchmarks, over current versions of ILS.

Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic

In this paper, an architectural framework for post-silicon tuning of nanoscale CMOS circuits is developed. The tuning methodology is driven by a ¿tunable¿ gate design that allows the gate to be switched from a high-speed/high-power mode to a low-speed/low-power mode under digital control. A small number of ¿critical¿ logic gates are replaced with tunable gates for post-silicon power-performance tuning. In addition, supply voltage and body bias can be employed as hardware ¿tuning knobs¿ as well to deal with delay and leakage variations. After silicon is manufactured, the hardware ¿knobs¿ are programmed through the use of an implicit self-test methodology that can be exercised by the proposed self-adaptation architectural framework. It is seen that the delay yield can be improved by an average of 40% with minimal impact on area.

A dual-Vt layout approach for statistical leakage variability minimization in nanometer CMOS

Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. In this paper, the problem of leakage power variation minimization in the presence of spatially correlated across-die process variations is addressed. It is shown that with minimal impact on delay, the placement of low-Vt gates in a layout can be performed in such a way to maximize the yield for a specified leakage power upper bound. For the obtained placement of low Vt gates, the layout can then be optimized for other important criteria such as wire length. Simulation of across-die variations for ISCAS benchmarks is performed and guidelines for distributing the low-Vt gates across the die are developed.

Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS

End-of-the-roadmap nanoscale CMOS is expected to suffer from significant defectivity due to manufacturing defects, random process variations, and wear-out during normal operational. To ensure acceptable yield and reliable operation of the circuit during its life-time, future circuits must be equipped with significant defect-tolerance capabilities. Traditional defect-tolerance approaches are too expensive to be applied to general purpose circuits. In this paper, we propose a defect-tolerant CMOS logic gate architecture that exploits the inherent functional redundancy in static CMOS. This is accomplished by reconfiguring the CMOS logic gate to a pseudo-NMOS-like gate in the presence of a defect. The resulting defect-tolerant logic architecture incurs only a modest area overhead. The proposed gate design can tolerate defects in either the pull-up or pull-down network of the gate. The architecture can tolerate multiple defects across the logic gates of a CMOS logic circuit. The effectiveness of the proposed defect tolerance technique and its impact on circuit delay and power is studied. It is shown that the technique imposes little delay overhead (less than 6%) but incurs power dissipation overhead (less than 20%) in the presence of defects.