Masaaki Sugimoto

Application of a bitmap analysis system to the forefront of DRAM devices development

A bitmap analysis system with a shape classification has been developed for use in manufacturing of forefront DRAM devices. This system shortens the time needed to improve the processing conditions according to the results of failure analysis. This system is a part of a total yield enhancement system have already been put to practical use in mass production.

Yield enhancement using a memory expert system linked to the wafer inspection tool

This paper describes a memory yield enhancement system that allows rapid determination of problematic wafer processing steps during mass production. Previously, we had developed an expert system that, in addition to generating the defect statistics, can quickly predict a faults cause as well as the processing step with the high probability of being responsible for the cause with 40 seconds for a 16 M DRAM. The system discussed in this paper combines our expert system with a conventional, stand-alone cell-to-cell comparison-based wafer inspection tool via an innovative software link. Comparison of wafer mappings, produced independently by the expert system and the wafer inspection tool, enables fast confirmation of the expert systems predictions. As a result, a production engineer can quickly recognize the corrective action to take to prevent the recurrence of the defect for the process step concerned. Use of this system has allowed quick identification of the cause of actual low yield circumstances.