Tohru Tsujide

VLSI fault localization using electron beam voltage contrast image : novel image acquisition and localization method

Novel methods have been developed concerning voltage contrast image acquisition using the electron beam tester, and concerning fault searching on a VLSI chip, and have been applied to real faults of VLSI devices. The developed voltage contrast image acquisition method has been shown to have acquisition time about thousand times faster than that of the conventional stroboscopic method. The strategy used in searching is that of tracing back upstream of the fault by referring to the voltage-contrast-subtracted image. This strategy is more effective than the conventional dynamic fault imaging (DFI) method where all the images on the entire chip area and all test vectors are acquired. The results showed that the location time was five times or more shorter than using conventional location methods such as electron beam waveform measurement with the aid of a computer aided design (CAD) database.

C-V Shift Characteristics of Metal-Al2O3-Si and Metal-Al2O3-SiO2-Si Structures

C-V shift characteristics of MAS(Metal/Al2O3/Si) structure with Al2O3 prepared by the hydrolysis of AlCl3 are investigated as a function of the Al2O3 thickness, the temperature and the applied pulse width. Using also MAOS(Metal/Al2O3/SiO2/Si) structure the critical voltage required to shift the C-V curve is given as a function of the SiO2 thickness. The results show that the critical voltage of MAOS structure increases in proportion to the SiO2 thickness over the range 0?700? for negative bias and in the range 80?700? for the positive bias. Liquid such as Hg and diluted H3PO4 is used as an electrode as a substitute for metal. This Liquid/Al2O3/Si structure is not found to exhibit the positive C-V shift for the negative bias case. A qualitative explanation responsible for the C-V shift characteristics of MAS and MAOS structures is presented from these experimental results.

Memory failure analysis using EB voltage contrast image

This paper presents some novel fault localization techniques for a memory LSI by using an EB tester. Effective techniques for applying pulse combinations of input signals and acquiring images are put forward. Excellent voltage contrast images are acquired on the passivated devices without degradation of voltage contrast from charge up. Signal lines are back-traced by comparing good and bad images to identify the failure point. Application to the failure analysis of DRAMs is successfully performed with minimal time requirements.

An in-line process monitoring method using electron beam induced substrate current

In-line process monitoring technology plays a vital role in accelerating yield ramps and quickly identifying and resolving yield excursions in the system on a chip era. We have developed an in-line process monitoring method that uses electron beam induced substrate current. It is especially suitable for deep contacts and via holes. This method makes it possible to monitor non-destructive contacts and the via-hole formation process with a hole-bottom nm-order SiO2 film thickness measurement and a hole-bottom diameter measurement. Moreover, it allows us to evaluate etching-process variation over an 8-inch wafer in less than 20 min. The results can be used for in-line device sorting as well as for decisions regarding the timing of etching machine maintenance.

An Instability of MAOS Structures

An instability of metal-aluminum oxide-silicon dioxide-silicon (MAOS) structures is investigated by the capacitance-voltage characteristics. Furthermore, experiments are examined for MAOS structures obtained by annealing in the various ambients, and also compared with metal-aluminum oxide-silicon (MAS) and metal-aluminum oxide-silicon nitride-silicon dioxide-silicon (MANOS) structures. The new instability of a minor shift of the flat band voltage, displayed as a small negative (positive) shift in the flat band voltage under a positive (negative) bias, is observed in MAOS structures, and can be attributed to the polarization effect in AlxSiyOz layer, between silicon dioxide and aluminum oxide films, formed during the deposition of aluminum oxide film onto silicon dioxide film on silicon and during the annealing in oxygen or air.

Early LSI mass production - fast yield improvement and Si debugging

Failure analysis plays a very important role in the early introduction and fast yield improvement of new generation LSIs. We have developed novel failure analysis technologies including an expert-system-based memory cell failure cause identification system, which is linked to a particle or defect monitoring tool, as well as failure location isolation systems for memory peripheral circuitry and logic LSIs. This paper reviews all these technologies and introduces some examples of their implementation.