Masafumi Nogawa

A 10 Gb/s burst-mode CDR IC in 0.13 /spl mu/m CMOS

A 10 Gb/s burst-mode CDR (clock and data recovery) IC, that is eight times faster than previous burst-mode ICs, is fabricated in a 0.13 /spl mu/m CMOS process. It amplifies an AC-coupled input burst by means of an edge detection technique, and extracts a clock within 5 UIs with a gated oscillator. It consumes 1.2 W from a 2.5 V supply.

A 16.3-GHz 64:1 CMOS frequency divider

A new high-speed dynamic CMOS frequency divider that operates at frequencies of over 16 GHz is proposed. The core of the proposed 2:1 divider consists of only three inverters and one transmission gate, and it has no DC current. Using the 2:1 divider, we developed a 64:1 divider with 0.2-/spl mu/m CMOS/SIMOX technology. Experimental results show that the maximum input frequency of the proposed divider is 1.4 times as high as that of a conventional one. The proposed 64:1 divider has a high input frequency of 16.3 GHz with a power consumption of 45 mW at 2.0-V power supply, and a low power consumption of 2.0 mW with a input frequency of 7.0 GHz at 0.8-V power supply.

High-speed circuit technology for 10-Gb/s optical burst-mode transmission

A careful choice of burst-mode 3R receiver circuits achieves fast settling of 200 ns and low power of 1.68 W as well as the optical sensitivity and dynamic range in the 10G-EPON specification.

A 12.5Gb/s CMOS BER test using a jitter-tolerant parallel CDR

Implemented in a 0.13 /spl mu/m CMOS process, pulse pattern generation and BER test functions are integrated in a chip. A parallel CDR (clock data recovery) circuit provides 12.5 Gb/s operation and wide tolerance of over 0.5 UIpp for 4 to 80 MHz sinusoidal jitter.

10.3-Gb/s burst-mode CDR with idle insertion and digital calibration in 40-nm CMOS for 10G-EPON systems

A burst-mode CDR (B-CDR) suffers from a trade-off between jitter transfer and lock time. To solve the trade-off, we utilize a continuous-mode CDR (C-CDR) after a B-CDR with converting the burst signal to the quasi-continuous signal by idle insertion. The B-CDR, designed in 40-nm CMOS, also employs a fully digital, 6-bit automatic frequency calibrator for compensating the process variation. It calibrates the oscillation frequency of the VCO in the B-CDR from 10.3 GHz ± 2 GHz to 10.3 GHz ± 60 MHz. The B-CDR, integrated with the C-CDR, achieves output-data-jitter reduction of 17.3 dB at jitter frequency of 300 MHz and lock time of 220 ns, complying with the 10G-EPON standard.

A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13/spl mu/m CMOS

A 10Gb/s burst-mode limiting amplifier is developed in a 0.13mum CMOS process. An adaptive gain-selection technique achieves a settling time of 0.8ns and a wide input dynamic range of 28dB, which is five-times wider than that of previous work at 10Gb/s

A 56-Gb/s Transimpedance Amplifier in 0.13-µm SiGe BiCMOS for an Optical Receiver with -18.8-dBm Input Sensitivity

This paper describes a 56-Gb/s transimpedance amplifier with a level-shift circuit and double-feedback-loop (DFB) compensation architecture to achieve high input sensitivity. The level-shift circuit placed between a main transimpedance amplifier and a post amplifier mitigates the trade-off between the bandwidth and noise of the receiver, which reduces the input referred noise by 70%. The DFB compensates for process variation without increasing the noise. The transimpedance amplifier was fabricated in 0.13-um SiGe BiCMOS technology and packaged with an avalanche photodiode. The 3-dB bandwidth of 38.4 GHz and the input referred noise current density of 14.8 pA/rtHz are achieved. These are the best performance among published 50-Gb/s-class transimpedance amplifiers for optical communication.

A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking

We propose a low-power and compact 25-Gb/s differential CMOS modulator driver. To achieve low power consumption, we employ an output driver with a high-gain single-stage amplifier and a gainless pre-driver with an equalizer function. In the pre-driver, we use area-efficient 3D inductors for the inductor peaking technique to obtain the equalizer function with compactness. We also employ a cascode amplifier consisting of high-voltage and standard MOSFETs to output a large voltage swing in CMOS technology. The proposed driver was fabricated in 65-nm 1P9M standard CMOS. It exhibits a data rate of 25 Gb/s, a differential output swing of 3.3 Vpp with an input swing of 300 mVpp, and power consumption of 480 mW with 1.2-/3.3-V dual supplies. The active area is only 0.029 mm2, including all inductors. The results indicate that the best power efficiency, which is 26 % better than the state of the art, and good power consumption versus output swing FoM (mW/Vpp) are achieved.

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect levelvarying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-μm CMOS process. It successfully operates at a data rate of 10.3125Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2ns with AC-coupling without a reset signal. The IC also demonstrates 1001bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

A 2.25-mW/Gb/s 80-Gb/s-PAM4 linear driver with a single supply using stacked current-mode architecture in 65-nm CMOS

This paper presents a low-power linear driver for a coherent optical transmitter. We propose a driver using stacked current-mode architecture to achieve low-power consumption with a single supply. The driver can drive from 25 to 50 Ω impedances with almost the same output waveforms by using a variable equalizer and adjusting the current of the post-amplifier. The proposed driver was fabricated in 65-nm CMOS technology and achieved the power efficiency of 3.6 mW/Gb/s with a differential output swing of 2.9 Vpp for a 50-Gb/s NRZ signal and 2.25 mW/Gb/s with a differential output swing of 2.0 Vpp for an 80-Gb/s PAM4 signal.