Shinsuke Nakano

A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking

We propose a low-power and compact 25-Gb/s differential CMOS modulator driver. To achieve low power consumption, we employ an output driver with a high-gain single-stage amplifier and a gainless pre-driver with an equalizer function. In the pre-driver, we use area-efficient 3D inductors for the inductor peaking technique to obtain the equalizer function with compactness. We also employ a cascode amplifier consisting of high-voltage and standard MOSFETs to output a large voltage swing in CMOS technology. The proposed driver was fabricated in 65-nm 1P9M standard CMOS. It exhibits a data rate of 25 Gb/s, a differential output swing of 3.3 Vpp with an input swing of 300 mVpp, and power consumption of 480 mW with 1.2-/3.3-V dual supplies. The active area is only 0.029 mm2, including all inductors. The results indicate that the best power efficiency, which is 26 % better than the state of the art, and good power consumption versus output swing FoM (mW/Vpp) are achieved.

A 2.25-mW/Gb/s 80-Gb/s-PAM4 linear driver with a single supply using stacked current-mode architecture in 65-nm CMOS

This paper presents a low-power linear driver for a coherent optical transmitter. We propose a driver using stacked current-mode architecture to achieve low-power consumption with a single supply. The driver can drive from 25 to 50 Ω impedances with almost the same output waveforms by using a variable equalizer and adjusting the current of the post-amplifier. The proposed driver was fabricated in 65-nm CMOS technology and achieved the power efficiency of 3.6 mW/Gb/s with a differential output swing of 2.9 Vpp for a 50-Gb/s NRZ signal and 2.25 mW/Gb/s with a differential output swing of 2.0 Vpp for an 80-Gb/s PAM4 signal.

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS

A 25-Gb/s half-rate clock and data recovery (CDR) IC using a current-mode logic (CML) buffer circuit with a latch load circuit for delay generation is presented. To achieve low-power operation of the CDR, the latch-load circuit for delay generation is combined with a CML buffer circuit, which provides a wide controllable delay range. This enable a reduction in the number of the CML circuits for delay generation used in the CDR IC. To confirm the validity of the proposed method, we fabricated a 25-Gb/s half-rate CDR IC with the 65-nm CMOS process. The power consumption of the proposed circuit is around half that of the conventional half-rate CDR circuit The area for the core circuits is 0.09 mm2, and the power consumption without output buffers is 96mW.

Simulation of high-speed CMOS inverter-based driver for silicon photonic segmented Mach-Zehnder modulator

We propose a high-speed and power-efficient CMOS-inverter-based driver for a silicon photonics-based segmented Mach-Zehnder modulator (MZM). The proposed driver is equipped with area-efficient three-dimensional inductors, which are suitable for flip-chip assembly with a compact area and for inductive peaking to increase the data rate. We also employ a dual-drive push-pull configuration to drive the MZM with large voltage swing in 65-nm CMOS technology. The simulated power consumption of the proposed CMOS driver is 110 mW with 1.1-/2.2-V dual voltage supplies for an output swing of 4.0 Vppd and 40-Gb/s operation. The active area of the designed CMOS driver chip is only 230 × 280 µm2, including all the inductors. We also designed a segmented MZM with two 500-µm sections, and simulated the extinction ratio of the designed MZM with the driver is 2.4 dB at 40-Gb/s.

20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters

We propose a low-power millimeter-wave ultra-wideband impulse radio (UWB-IR) transmitter using an on/off keying (OOK) pulse modulator for wireless connection or dielectric-waveguide interconnects. To achieve low-power consumption, we use a low-power OOK pulse modulator consisting of only four CMOS inverters and passive elements. The proposed transmitter was fabricated in 65-nm CMOS technology. It exhibits the maximum data rate of 8 Gbps, output power of -15.6 dBm, power consumption of 20.1 mW, and power efficiency of 2.5 mW/Gbps at an operating frequency of 50 GHz.