Masahiko Fujisawa

Low-resistive and homogenous NiPt-silicide formation using ultra-low temperature annealing with microwave system for 22nm-node CMOS and beyond

A novel NiPt-silicide formation using microwave annealing (MWA) is proposed, and superior properties of NiPt silicide in ultra-shallow junction (USJ) are demonstrated for the first time. MWA is suitable for the thin NiPtSi formation with its stable and ultra-low temperature (less than 250 °C) heating. The anomalous Ni diffusion during the NiPtSi formation is considered to be suppressed because MW system heats Si substrates selectively. As a result, low-resistive and homogeneous NiPtSi can be formed, and the increase of the junction leakage current due to the abnormal NiPt-silicide growth is successfully suppressed in USJ. This superior technique is quite promising for achieving 22nm-node CMOS and beyond.

Extremely Low Keff (1.9) Cu Interconnects with Air Gap Formed Using SiOC

Dual damascene Cu interconnects with Keff below 2.0 have been demonstrated for the first time. Air gaps between Cu lines were formed with a low K SiOC film in a carefully designed manner. CoWP cap layers were introduced to protect the Cu lines and to eliminate a dielectric liner layer. In addition, AGE (Air Gap Exclusion) was applied to solve crucial problems related to the air gaps. Keff of 1.9 was obtained at 65 nm design rule, which surpassed by far ITRS target (2.5~2.8) for hp 45. It was also confirmed that leakage current between lines was suppressed by the formation of the air gaps.

NiPt silicide agglomeration accompanied by stress relaxation in NiSi(010) ∥ Si(001) grains

Pt-doped Ni (NiPt) silicide agglomeration in terms of NiSi crystal orientation, Pt segregation at the NiSi/Si interface, and residual stress is studied for the first time. In the annealing of Ni monosilicide (NiSi), the growth of NiSi grains whose NiSi b-axes are aligned normal to Si(001) [NiSi(010) ∥ Si(001)] with increasing Pt segregation at the NiSi/Si interface owing to a high annealing temperature was observed. The residual stress in NiSi(010) ∥ Si(001) grains also increases with increasing annealing temperature. Furthermore, the recrystallization of NiSi(010) ∥ Si(001) grains with increasing residual stress continues through additional annealing after NiSi formation. After the annealing of NiSi(010) ∥ Si(001) grains with their strain at approximately 2%, the start of NiPt silicide agglomerates accompanied by stress relaxation was observed. This preferential recrystallization of NiSi(010) ∥ Si(001) grains with increasing residual stress is considered to enhance the NiPt silicide agglomeration.

Highly Reliable Cu Interconnect Using Low-Hydrogen Silicon Nitride Film Deposited at Low Temperature as Cu-Diffusion Barrier

We demonstrated highly reliable Cu interconnects using a high-quality silicon nitride film grown at temperatures below 300 °C. The low-temperature silicon nitride (LT-SiN) film, which was used as a Cu-diffusion barrier layer and a final passivation layer, was deposited at 275 °C by plasma-enhanced chemical vapor deposition at a low SiH4 flow ratio. The low SiH4 flow ratio was due to the use of a highly dilute nitrogen flow, leading to the generation of many nitrogen radicals or ions in the plasma. These radicals or ions might reduce the hydrogen concentration and defect density of the film. As a result, a stoichiometric silicon nitride (Si3N4) film with a low hydrogen concentration was successfully obtained. By applying this LT-SiN film in 130-nm-node Cu interconnects for magnetoresistive random access memory, highly reliable via-hole electromigration (Via-EM) and line-to-line time-dependent dielectric breakdown (TDDB) characteristics were obtained.

Investigation of implantation damage recovery using microwave system for defect-less p-n junction

Advanced junction technology aiming at defect-less p-n junctions has been studied for the integration of ultimately scaled logic CMOS and non-digital functionalities. It is featured by low-temperature microwave annealing (MWA). We demonstrate that MWA effectively repairs ion-implantation damage without the excessive dopant diffusion in CMOS. This technology is promising for implementing high-performance logic CMOS and highly-functional non-digital components on one chip.

Structure-Modification Model of Porogen-Based Porous SiOC Film with Ultraviolet Curing

The effect of ultraviolet (UV) curing on film properties of porogen based porous SiOC (P-SiOC) film was investigated. The P-SiOC films were prepared by plasma-enhanced chemical vapor deposition (PECVD) using alkoxysilane and porogen (hydrocarbon). UV curing time was changed from 0 s to 1000 s. The variation of the k value and elastic modulus on the P-SiOC film with UV curing can be classified into three phases. From the behavior of pore density and free volume rate evaluated by using positron annihilation spectroscopy (PAS), the multiphase model for structural modification of P-SiOC film by UV curing was proposed. In addition, the optimum UV curing time for obtaining a superior P-SiOC film with lower k value and higher mechanical strength was determined.

Analytical Approach for Enhancement of n-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Performance with Carbon-Doped Source/Drain Formed by Molecular Carbon Ion Implantation and Laser Annealing

Enhancement of n-channel metal–oxide–semiconductor field-effect transistor (nMOSFET) performance with a carbon-doped source/drain (Si:C-S/D) was approached analytically for the first time. Si:C-S/D was formed by molecular carbon (C7Hx) ion implantation and laser annealing. C7Hx implantation forms a smooth interface between Si:C layers and Si substrates, and laser annealing also achieves a high carbon concentration of substitution. The channel strain with Si:C-S/D was successfully measured by UV Raman spectroscopy using a particular test pattern. The thick Si:C-S/D layer and the high carbon concentration of substitution produce a large strain at the channel region. It was confirmed that the performance of nMOSFETs is effectively improved by strained Si:C-S/D. These analytical approaches are quite valuable for promoting the development of strained nMOSFETs with Si:C-S/D.

Highly reliable 45-nm-half-pitch Cu interconnects incorporating a Ti/TaN multilayer barrier

A Ti/TaN multi-layer can achieve a highly reliable Cu interconnect with a porous SiOC (ELK; k < 2.5) structure. Ti shows good wettability with Cu and unique properties with extreme low-k (ELK)-structured interconnects. On the other hand, Ta is known to be an effective barrier to Cu diffusion. We confirmed that the Ti barrier is different from the Ta barrier from the viewpoint of metal-oxide behavior and improved electromigration (EM) and stress migration (SM). In addition, the time-dependent dielectric breakdown (TDDB) characteristic can be improved by using a Ti barrier combined with a TaN barrier.

Characterization of MOS transistors after TSV fabrication and 3D-assembly

Room-temperature bonding by means of mechanical caulking to electrically interconnect stacked chips using through-silicon vias can greatly reduce process cost. We have already demonstrated the feasibility of this approach in several test samples. However, in a three-dimensional system-in-package sample containing a commercially available microcomputer unit, we encountered some difficulties in manufacturing TSVs in a high-yield ratio. To overcome these difficulties and thereby achieve high-yield TSV fabrication in our process, we devised a new electrode structure. By connecting the TSVs to internal copper lands formed at the back-end metal layers, we achieved a high-yield TSV fabrication of more than 99 %. To evaluate the impact of the TSV processing and proximity on MOS transistor performance, we measured the drain saturation current (IDSAT) in MOS transistors. The MOS transistors operated successfully without any degradation of performance in both the post-processing of TSVs and the post-assembly by mechanical caulking at room temperature.

Cu Dual-Damascene Interconnects with Direct Chemical Mechanical Polishing Process on Porous Low-k Film

To reduce the effective dielectric constant (keff) value for 32 nm node technology and beyond, the effects of a direct chemical mechanical polishing (CMP) process on porous low-k film without a protective cap layer were investigated. It was confirmed that a capless structure on porous low-k film is effective in reducing the resistance–capacitance (RC) products, but it causes degradation of wire-to-wire breakdown voltage characteristics. The most important point of a direct CMP process is to control the amount of damage to the polished surface. In this study, two types of low-k film were compared in combination with a variety of CMP process conditions. As results, we found that a direct CMP process has a positive effect on wire-to-wire current leakage and time-dependent dielectric breakdown (TDDB) reliability where a porous low-k film deposited by modified conditions is used. By optimizing the deposition and curing conditions, it is possible to control the distribution of different pore sizes in porous low-k film, which allows us to realize a highly reliable capless structure.