Masazumi Matsuura

A highly reliable self-planarizing low-k intermetal dielectric for sub-quarter micron interconnects

In this paper we present a highly reliable IMD process using a new CVD chemistry. The key to the process is a unique gas chemistry of methylsilane and hydrogen peroxide, resulting in excellent gapfill and planarity with low-k of 2.75. Via-chain resistances using this process are just as low and stable as those using inorganic IMDs. This is likely attributable to the smaller amount of water outgassing with this process.

Film characteristics of APCVD oxide using organic silicon and ozone

Film characteristics of APCVD oxide using octamethylcyclo tetrasiloxane (OMCTS) and O3 (AP-OMCTS oxide) have been investigated minutely for applications to advanced VLSI devices. Deposition characteristics of AP-OMCTS oxide strongly depend on deposition temperature and high quality films can be formed by increasing the deposition temperature. The step coverage shows a most smooth flowing profile around at 425°C. The dependence of the deposition characteristics on O3 concentration can not be observed in contrast with the deposition characteristics of AP-TEOS oxide which evidently depend on the O3 concentration. From these results, it is supposed that CVD reactions based on OMCTS-O3 chemistry consist of the precursor production correspond to CH3 elimination reaction with O radicals and the subsequent polymerization (dehydration) caused by thermal energy provided from hot substrate.

Low-temperature APCVD oxide using TEOS-ozone chemistry for multilevel interconnections

A low-temperature APCVD (atmospheric-pressure chemical vapor deposition) process using TEOS-O/sub 3/ chemistry has been investigated as an interlayer dielectric application technique for multilevel interconnections. The deposition rates depend on the substrate materials, and the oxide films self-planarize the underlying topography, exhibiting smooth flowing profiles of step coverage as deposited. High-quality films can be formed by increasing the deposition temperature and the O/sub 3//TEOS ratio, and much more improvement can be achieved by annealing. This process has been successfully applied to submicron devices.<<ETX>>