Takashi Akioka

A 6-ns 256-kbit BiCMOS TTL SRAM

A 6-ns 64K*4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm*10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T/sub a/=25 degrees C, V/sub CC/=5 V with a 30 pF load connected to the common I/O node.<<ETX>>

A 6-ns 256-kb BiCMOS TTL SRAM

The authors describe a 256-kb BiCMOS transistor-transistor logic (TTL)-compatible static RAM (SRAM) with typical address access time of 6 ns (5.0 V, 25 degrees C). The fast access time is due to the combination of new circuits and double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The high performance of the SRAM is due to the new BiCMOS circuit technologies. These include: (1) a low-input-capacitance BiCMOS gate, which reduced the gate loads in a decoder; (2) a reduced-load multiplexer-line sense amplifier; and (3) the two-level-presetting architecture of the TTL output buffer, which reduced the output-drive-current change rate to 20 mA/ns for a *8-b configured chip with a propagation delay time of 1.5 ns. The current change rate is about half that of the conventional-type output buffer. The fabricated SRAM is 4.25 mm*10 mm. >

Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v

We describe new circuit techniques for an 8-11s ECL compatible 16Mb BiCMOS SRAM. This is the first reported implementation of ECL lOOK U0 compatibility with an operation voltage of less than 3.0V. We developed an ECL reference circuit that operates with a 2.3V supply voltage. A novel hierarchically divided common-emitter sense circuit reduces the delay due to long data lines to achieve a simulated address access time of 8ns under typical operating conditions.

Memory circuits and technology

There are many memory technologies that are competing to become the mainstream nonvolatile memory solution. This session presents circuits and technology for some of these emerging memories, including ferroelectric RAM and phase change RAM. State-of-the-art design and testing techniques for 6T CMOS SRAM, novel architecture and circuit techniques for content addressable memories (CAMs) are also presented. Our first paper, by the well-known Dr. Kinam Kim, opens the session with a presentation of emerging memories. He investigates the performance, scalability and technical barriers of ferroelectric RAM (FeRAM) and phase-change RAM (PCRAM). The second paper describes novel design techniques for FeRAM, which facilitate a high reliability 8Mbit 1T1C memory with 0.71µm 2 cell. The third paper describes a PCRAM that operates at the lowest voltage ever published, 1.5V, as a CMOS memory array, using phase-change material of the lowest RESET current. The fourth paper proposes a capacitor-less twin-transistor RAM (TTRAM) that has fast access time and is fully compatible with a CMOS SOI process. The next two papers address the issue of static noise margin of advanced CMOS SRAM that is getting increasingly more important with the scaling of MOS dimensions. The fifth paper proposes a fast and accurate method to estimate failures in a SRAM, caused by random dopant fluctuation. Reliable and economical SRAM cell stability testing is an important issue in manufacturing SOCs with large embedded SRAMs. The sixth paper proposes reliable cell stability testing techniques with programmable pass/fail threshold. The last two papers discuss various issues in the design of a CAM. The seventh paper discusses new circuit techniques that reduce inherent noise of an embedded CAM, which achieved significant reduction in peak power supply noise. The last paper describes a novel ternary CAM (TCAM) architecture, which stores entry data in an associated embedded DRAM array as well as in a TCAM array. It allows significant improvement of soft-error immunity over a conventional architecture, at the cost of the additional DRAM.