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Featured researches published by Masahisa Ose.


electronic components and technology conference | 2012

Newly developed ultra low CTE materials for thin core PKG

Masato Miyatake; Hikari Murai; Shin Takanezawa; Shinji Tsuchikawa; Masaaki Takekoshi; Tomohiko Kotake; Masahisa Ose

To achieve the recent improvements in miniaturization and performance of mobile devices (Smart phone, Tablet PC etc.), the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. However, the thinner PKG substrate may cause poor connection reliability due to increased warpage by soldering. The ultra low CTE (Coefficient of thermal expansion) core material has been required as the key solution for the reduction of the warpage of the thinner PKG substrate such as PoP (Package on package). We have just developed two types of ultra low CTE core materials named E-705G and E-800G to meet with the requirement, applying our original resin systems and the filler surface treatment technologies. The developed materials show the ultra low CTE(X, Y) property (2.8-3.3 ppm/°C) similar to that of glass fabric itself. Also E-705G has high flexural modulus over 33-36 GPa at room temperature. Regarding E-800G, it has the good dielectric characteristics (lower dielectric constant and dissipation factor), can be applicable higher speed PKG. Both of the materials have high reliability and high heat resistance which is suitable for the lead-free soldering process. Confirming the warpage property, we evaluated the warpage behavior of PoP (bottom) constructions before/after assembly process. The newly developed materials showed the much lower warpage than the conventional low CTE material.


electronic components and technology conference | 2014

Ultra low CTE (1.8 ppm/°C) core material for next generation thin CSP

Tomohiko Kotake; Hikari Murai; Shin Takanezawa; Masato Miyatake; Masaaki Takekoshi; Masahisa Ose

Along with the advancement in miniaturizing of mobile devices, typified by smart phones and tablet PCs, the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. As one of the most innovative solutions, the PoP (package on package) technology, which has the three-dimensional construction, has been expanding rapidly in recent years. However, the thinner PKG such as PoP tends to warp at the assembly process and cause the decrease in the connection reliability. Therefore ultra low CTE (coefficient of thermal expansion) core materials have been needed as a key solution for the reduction of the warpage for PoP. Recently, we have developed new ultra low CTE core material named E-770G for next generation thin CSP, applying new resin systems, featuring low shrinkage and low residual stress. In particular, E-770G has achieved ultra low CTE of 1.8 ppm/°C which leads to significant reduction of the warpage. Furthermore, it has low dissipation factor at high frequencies (Df: 0.005 at 1 GHz). So its also applicable to high speed PKG applications. Confirming the warpage property, we evaluated the warpage behavior of the bottom PKG before/after assembly process. E-770G showed the much lower warpage than the conventional ultra low CTE core material.


cpmt symposium japan | 2013

New ultra low CTE material to reduce the warpage of thinner PKG

Tomohiko Kotake; Hikari Murai; Shin Takanezawa; Masato Miyatake; Masaaki Takekoshi; Masahisa Ose

Along with the advancement in miniaturizing of mobile devices, typified by smart phones and tablet PCs, the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. As one of the most innovative solutions, the PoP (package on package) technology, which has the three-dimensional construction, has been expanding rapidly in recent years. However, the thinner PKG substrate tends to warp at the assembly process and cause the decrease in the connection reliability. Therefore ultra low CTE (coefficient of thermal expansion) materials have been needed as a key solution for the reduction of the warpage for thinner PKG substrates. Recently, we have developed new ultra low CTE material named E-770G for next-generation semiconductor PKG substrate, applying new resin systems, featuring low shrinkage and low residual stress. In particular, E-770G has achieved ultra low CTE (X) of 1.8 ppm/°C which leads to significant reduction of the warpage. Furthermore, it has low dissipation factor at high frequencies (Df: 0.005 at 1 GHz). So its also applicable to high speed PKG applications. Confirming the warpage property, we evaluated the warpage behavior of thinner PKG substrate before/after assembly process. E-770G showed the much lower warpage than the conventional ultra low CTE material.


international conference on electronic materials and packaging | 2008

New halogen-free laminate for advanced package substrate

Takahiro Tanabe; Tetsuro Irino; Masahisa Ose; Kazunaga Sakai

Nowadays, the demand for the printed wiring board (PWB) of the environment harmony type is rising rapidly. We have developed a new halogen-free material with low coefficients of thermal expansion (CTE), which will be applied to the plastic packages such as FC-BGA and CSP. The original resin system and filler treatment technique named FICS (filler interphase control system) were applied to the material. The newly developed halogen-free material named MCL-E-679FG(S) has a higher glass transition temperature (Tg), peel strength, and heat resistance than the conventional halogen-free materials. Their properties are advantageous to the melting temperature rise of the lead-free solder. Another newly developed halogen-free material named MCL-E-679GT has the lower CTE combined with standard glass fabric (E-glass). It has been developed by new resin system. Its advantage is to reduce of PKG warpage, such as package on package (PoP), during the heat process for the chip mounting. In order to meet fine-line formation, we developed profile-free copper foil. With the copper foil of 18 mum thickness, we have formed the fine line of 60 mum or less pitch by the conventional subtractive method. It will be effective for advanced package substrate such as high density CSP.


Archive | 2000

Prepreg, metal-clad laminate, and printed circuit board obtained from these

Nozomu Takano; Tomio Fukuda; Masato Miyatake; Masahisa Ose


Archive | 2002

PREPREG, METAL-CLAD LAMINATED PLATE AND PRINTED WIRING PLATE USING THE SAME

Shuji Aitsu; Masahisa Ose; 周治 合津; 昌久 尾瀬


Archive | 2000

Prepreg, metal-clad laminated board, and printed wiring board using prepreg and laminated board

Tomio Fukuda; Masato Miyatake; Masahisa Ose; Mare Takano; 正人 宮武; 昌久 尾瀬; 富男 福田; 希 高野


Archive | 2006

Resin composition, prepreg using the same, flame-retardant laminate and printed wiring board

Akira Kato; Masato Miyatake; Masahisa Ose; Shinji Shimaoka; 亮 加藤; 正人 宮武; 昌久 尾瀬; 伸治 島岡


Archive | 2001

Resin composition and flame-retardant laminate board and printed wiring board using the composition

Tomio Fukuda; Masato Miyatake; Masahisa Ose; Shinji Shimaoka; Ikuo Sugawara; 正人 宮武; 昌久 尾瀬; 伸治 島岡; 富男 福田; 郁夫 菅原


Archive | 2001

PREPREG FOR PRINTED CIRCUIT BOARD AND METAL-CLAD LAMINATE

Tomio Fukuda; Masato Miyatake; Yasuhiro Murai; Masahisa Ose; Hiroshi Sakai; Shinji Shimaoka; Ikuo Sugawara; 正人 宮武; 昌久 尾瀬; 伸治 島岡; 康裕 村井; 富男 福田; 郁夫 菅原; 広志 酒井

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