Masakazu Ehama

A 256mW full-HD H.264 high-profile CODEC featuring dual macroblock-pipeline architecture in 65nm CMOS

A video-size-scalable H.264 high-profile CODEC including 19 specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two parallel pipelines for macroblock processing, the CODEC consumed 256 mW in real-time encoding of full-HD (1080i) video at an operating frequency of 162 MHz. It represents a 38% reduction in power consumption per pixel compared with state-of-the-art designs.

Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture

To solve recent pressing issues regarding satisfying numerous video codec standards and supporting “full-high-definition” (full-HD) (i.e., 1920 pixels by 1080 lines) video on different consumer devices, a multi-standard CODEC IP based on a heterogeneous multiprocessor architecture was developed. To achieve satisfactory performance with low power consumption, operation-specific processors were designed in regards to two types of processing: stream processing and pixel processing. The CODEC uses effectively several dedicated circuits for functions which are unsuitable for those processors. To design the CODEC, we developed a C-language model to check that the architecture worked correctly. The model was also used as a reference for verifying the RTL model. The CODEC can process full-HD videos formatted in H.264, MPEG-2, MPEG-4, and VC-1 at an operating frequency of 162 MHz.