Masakazu Soga

A fault‐tolerant combinational circuit with fault diagnosis capability—To mask and detect the loss of any one connection between gate circuits

We will produce a fault-tolerant circuit with fault diagnosis function by using neuron-MOS transistors. As to the fault range, we hypothesize a single disconnection fault in the wiring between gates. First, the inverter, AND gate, and OR gate are fault-tolerant implemented and the fault-tolerant logic gates with fault diagnosis mode are designed. Then, we will show that after optimally combining these fault-tolerant logic gates by the configuration of multiplication standard form, any fault-tolerant combinational circuit with fault diagnosis function can be obtained by multiplexing the result using interwoven logics. An ideal fault-tolerant combinational circuit with both fault masking function and fault detection function can be realized.