Masakazu Tokita

Die-to-database mask inspection with variable sensitivity

The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET started a 4-year project to reduce mask manufacturing cost and TAT by optimizing Mask Data Preparation (MDP), mask writing, and mask inspection in 2006, with the support from the New Energy and Industrial Technology Development Organization (NEDO). We report on the development of a new low cost mask inspection technology with short Turn Around Time (TAT), as a result of adopting a method of selecting defect detection sensitivity level for every local area, defined by such factors as defect judgment algorithm and defect judgment threshold, as one of the pseudo-defect-reduction technique necessary to shorten mask inspection TAT. Those factors are extracted from the database of Mask Data Rank (MDR) and converted on the basis of pattern prioritization determined at device design stage, using parallel computation.

Mask inspection system with variable sensitivity and printability verification function

We report on the development of a new mask inspection technology that makes total inspection faster and less costly. The new technology adopts a method of selecting a defect detection sensitivity level for every local area, defined by factors such as defect judgment algorithm and defect judgment threshold. This approach results in a reduction of pseudodefect count leading to shorter inspection and review time. Selected defect detection sensitivity levels for every local area are extracted from a database of Mask Data Rank (MDR) that is based on the design intent from the design stage, and/or on a pre-analysis of inspection pattern data. The proposed system also executes a printability verification function, not only for the mask defect regions but also for specific portions where high Mask Error Enhancement Factor (MEEF) is determined. It is necessary to ascertain suppression of pseudo-defect detection for extremely complicated masks such as masks with Source-Mask Optimization (SMO). This work reports on the new mask inspection system.

Defect printability analysis by lithographic simulation from high resolution mask images

We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer lithography model. This step leverages Brions industry-proven, hardware-accelerated LMC (Lithography Manufacturability Check) technology1. Existing litho process models that are in use for Brions OPC+ and verification products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge placement errors. The detection results on test and production reticles have been validated with AIMSTM.

Printability verification function of Mask Inspection System

In addition to the conventional demands for high sensitivities with which the mask inspection system detects the minute size defects, capability to extract true defects from a wide variety of patterns that should not be counted as pseudo defects has been quite demanding. It is necessary to ascertain suppression of MEEF incurred by the combination of parameters such as LER and defects of SRAF. NFT and Brion are jointly developing a mask-image based printability verification system with functions combining their respective technologies with the results from ASETs research. This report describes such defect detection results and introduces the development of a mask inspection system with printability verification function.

Concurrent optimization of MDP, mask writing, and mask inspection for mask manufacturing cost reduction

As the feature size of LSI shrinks the cost of mask manufacturing and turn-around-time (TAT) continues to increase. These increases are reaching to points of great concerns. Association of Super-Advanced Electronics Technologies (ASET) Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) launched a 4-year program for reducing mask manufacturing cost and TAT by concurrent optimization of MDP, mask writing, and mask inspection that involves exploitation of close relationships and synergism among them. The task will be accomplished by sharing four key avenues: a) common data format, b) clever use of repeating patterns, c) pattern prioritization based on design intent, and d) parallel processing. Under the concurrent optimization scheme, mask pattern priorities that we call as Mask Data Rank (MDR) are extracted from the design side, and repeating patterns are extracted from mask pattern data. These are fed-forward to mask writing and mask inspection sides. In mask writing, MDR is employed to optimize the writing conditions; and in Character Projection (CP) writing, repeating patterns are utilized for that purpose. In mask inspection, MDR is used to optimize defect judgment conditions, and repeating patterns are utilized for efficient review. For mask writing, we are developing a parallel e-beam writing system Multi Column Cell (MCC). Furthermore, we are developing an integrated diagnostic system for e-beam mask writer, and a technology for defect judgment technology based on defect printability in mask inspection. In this paper we describe details of our activity, its status, and some recent results.

Mask data rank and printability verification function of mask inspection system

With continued shrinkage of the semiconductor technology node, the inspection of mask with a single preset defect detection sensitivity level becomes impractical because of the increase occurrence of false capturing of defects. Inspection of leading-edge masks with conventional defect detection method, redundant detection of defects such as pseudo defects, or anomalies such as slightly deformed OPCs caused by assist features tend to increase the Turn Around Time (TAT) and cost of ownership (COO). This report describes a new method for the inspection of mask. It assigns defect detection sensitivity levels to local area inspections and is named as Regional Sensitivity Applied Inspection (RSAI). Then, the sensitivity information from each local area is converted into a format that can be fed into a Mask Data Rank (MDR) which is represented on the basis of pattern prioritization determined at the device design stage. Core technologies employing this concept resulted in the shortening of TAT where samples of actual device mask patterns were used. Printability verification functions (PVF) were applied to the advancement of technologies such as to Source Mask Optimization (SMO) technology. We report on the shortening of TAT that was achieved by the implementation of a new inspection technology that combines RSAI with MDR, and employs printability verification functions.

Mask-LMC: lithographic simulation and defect detection from high-resolution mask images

We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer lithography model. This step leverages Brions industry-proven, hardware-accelerated LMC (Lithography Manufacturability Check) technology1. Existing litho process models that are in use for Brions OPC+ and verification products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge placement errors. The detection result has been validated with AIMSTM.

A study of mask inspection method with pattern priority and printability check

The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET started a 4-year project to reduce mask manufacturing cost and TAT by optimizing Mask Data Preparation (MDP), mask writing, and mask inspection in 2006, with the support from the New Energy and Industrial Technology Development Organization (NEDO). Concerning the mask inspection, the project aims at shortening the review time after inspection. In mask inspection it approaches the limit to inspect the entire surface of a mask in the unique defect judgment algorithm without a pseudo defect. In addition, a nuisance defect including a pseudo defect increases by raising the defect detection sensitivity, and the review time after inspection increases. Mask inspection total time increases too and this will raise the mask inspection cost. Practical mask inspection can be conducted now by inputting the judgment level based on directions of design data there and by making a defect judgment level of every domestic area changeable. We can also shorten the review time by analyzing the printability on the wafer of the detected defect by the simulation, and by using the result for the defect judgment. In this report, we will show the latest research result about an inspection system technology that the defect judgment level for each domestic area can be changed, and a method to input the defect judgment level based on the pattern importance, which a device designer intended, into inspection equipment. In addition, we will show a design of the interface technology that hand over the information of the detected defect to a process simulator (wafer image simulator).

Advanced die-to-database inspection technique for embedded attenuated phase shift mask

We have developed a deep ultraviolet die-to-database inspection system MC-3500 for the 130 nm node and beyond. The system involves comparison of a mask image scanned at a wavelength of 257 nm and a reference data calculated from complex amplitude of objects with 200 Mpixel/s throughput. An approximation of Hopkins formulation in the region of a large partial coherence factor gives a nonlinear filtering scheme for embedded attenuated phase shift mask (EPSM). The nonlinear filtering was evaluated for intensity fidelity of the reference image using comparison with Hopkins formulation. Evaluation results show that phase optimization is effective in eliminating excessive image ringing and the minimum feature size to maintain fidelity is found to be over 3 pixels. The technique is promising in applications to high-transmission EPSM.

Electron-Beam Reticle Writing System For 16M Dram Class Devices

Based on our present understanding of the recent progress in optical technology, it appears that wafer steppers will be applicable for the production line up to 16M DRAM having 0.5 μm design rule or so. From this point of view, we have concluded that E-beam system promising the production of high quality reticles is mandatory necessary in the field. For the back-ground mentioned above, Toshiba has developed the new conceptual E-beam system designated EBM-160/80. This paper describes the design concept and system outline on EBM-160/80. The most essential requirements of this type of system, such as raster scan, round Gaussian beam and continuous moving stage, are to make CD increment smaller, simultaneously to get high production throughput and reasonable accuracy. Employing high speed bit data generating processor (HBG), we have completed high production throughput E-beam system which means throughput free from reticle pattern complexity. As a result, it takes about 40 min. at 0.25 μm address size or 250 min. at 0.1 pm address size for 5X, approx. 80 mm x 90 mm reticle with several millions of pattern. EBM-160/80 has capability to produce high quality reticle for up to 16M DRAM. In order to realize enough accuracy, the new technologies have been developed and integrated. As a result, we could achieve our accuracy target, butting accuracy 0.05 pm, CD control 0.1 μm, overlay accuracy 0.1 pm, scan linearity 0.05 μm.