Masaki Nakagawa

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit media embedded processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb system-in-silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 mum CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 mm2 die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.

A 1.41W H.264/AVC Real-Time Encoder SOC for HDTV1080P

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5 Gbps 64 Mb system-in-silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.18 m CMOS technology, the SoC core occupies 27.1 mm die area and consumes 1.41 W at 200MHz in typical work conditions.

DCT-based still image compression ICs with bit-rate control

The authors discuss compression and coding ICs for still images based on the DCT (discrete cosine transform) using a new algorithm for bit-rate control. The compression and coding method used in these ICs conforms to the JPEG (Joint Photographic Expert Group) standard. These ICs have been developed for a digital still camera system using memory cards as the recording medium, and they have a bit-rate control function to guarantee the number of images recorded on a card. The functional specifications and composition of these ICs, as well as the structure of the encoder IC, and details of the algorithm used for bit-rate control are considered. >

A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs

High-definition video applications, such as digital TV and digital video cameras, require high processing performance for high-quality visual images in addition to a complex video CODEC. Pre-/postprocessing to improve video quality is becoming much more important because requirements for pre-/postprocessing vary among applications and processing algorithms have not been stabilized. Therefore, a new processor architecture that has a highly parallel datapath is needed. In this paper, we introduce a VLIW vector media coprocessor, ldquovector coprocessor (VCP),rdquo that includes three asymmetric execution pipelines with cascaded SIMD ALUs. To improve performance efficiency, we reduce the area ratio of the control circuit while increasing the ratio of the arithmetic circuit. The total gate count of VCP is 1268 kgates and its maximum operating frequency is 300 MHz at 90-nm CMOS process. Some of the processing kernels in an adaptive prefilter that is applied to preprocessing for video encoding are evaluated. In the case of the edgeness and the sum of absolute differences, the performance is 183 giga operations per second. VCP offers enough performance for HD video processing and good cost-performance while all processing pipeline units operate effectively.

Digital still video camera using semiconductor memory card

A newly developed compact camera which can take digital still pictures by using a semiconductor IC memory card is described. The developed prototype is suitable for consumer use because of its easy operation and fully automatic functions. High-quality frame images are obtained with degradation-free data compression LSIs. The camera makes it possible to store 13 high-quality still pictures in a 20-Mb SRAM card by using a frame imaging frame interline transfer CCD and a data compression technique for ADPCM (adaptive differential pulse-code modulation). >

High Picture Quality Digital TV for NTSC and PAL Systems

A new digital TV for both the NTSC and the PAL systems has been developed. High picture quality was obtained by using a 2-line memory for the Y/C separation and the contour correction. Also, this digital TV is so designed that new features can be easily added to it.

Pack instruction generation for media pUsing multi-valued decision diagram

SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, multi-valued decision diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that our code generation technique can generate assembly code with SIMD and pack instructions performing complex repacking of 8 packed data in registers for a commercial VLIW processor with 6 pack instructions and achieved speedup ratio of up to 7.7.

A High Quality Digital TV Utilizing 2 CMOS Chips

We have developed the digital TV system IC line-up which consists of 2 MOS LSIs and 4 Bipolar ICs. Digital signal processing is carried out in 2 LSIs with 1.5um-rule CMOS technology, by which picture quality can be improved. It has been designed for both NTSC and PAL systems and it is adaptive for double-line scanning.