Masaki Okuno

Piezoelectric Characteristics of Chiral Polymer Composite Films Obtained under Strong Magnetic Field

It is difficult to obtain a drawn chiral polymer/inorganic material composite membrane with shear piezoelectricity by the conventional method because the chiral polymer/inorganic material composite membrane breaks during the drawing process by which shear piezoelectricity is realized. Using a strong magnetic field, we propose to manufacture a drawn composite membrane of poly-l-lactic acid (PLLA), a chiral polymer, and hydroxyapatite (Hap), an inoroganic material (PLLA/Hap composite membrane). The manufacturing method used here is effective for obtaining a drawn PLLA/Hap composite membrane with a large uniform area. Also, the shear piezoelectric constant of the drawn PLLA/Hap composite membrane is about 20 pC/N. This value is large for piezoelectric polymers.

Photo-Excited Cleaning of Silicon with Chlorine and Fluorine

Chlorine radicals generated with UV irradiation are effectively used to remove residual metal contaminants after vatious LSI processes. Aluminum, iron, and copper atoms are effectively removed as volatile chloride species from silicon surfaces. The mechanism has been studied using silicon wafers intentionally contaminated with those metal ions. Contaminants are involved in native oxides as metal oxides or hydroxides. Chlorine radicals penetrate the native oxides and attack those oxides or hydroxides vaporizing metal chlorides. The cleaning process is accompanied with slight etching of silicon surfaces to a depth as thin as a few nm. However, this is not essential because the substrate temperature is more important than the etching depth. Alkaline metals are also removed from the surfaces to the level as small as the detection limit of atomic absorption spectroscopy. We believe that those are removed through a lift-off process. The, wixture of fluorine and hydrogen gases removes a native oxide of silicon under UV irradiation. Hydrogen fluoride radicals react with native oxide resulting in hydrogen termination on silicon dangling bonds. These cleaning processes are advantageous for low temperature silicon epitaxy, reliable contact formation, and thin gate oxide growth.

A 45nm Low-Cost LSTP CMOS Technology with full NCS/dual-damascene Cu interconnects

A 45 nm low-cost LSTP CMOS technology is presented. This technology features advanced ArF lithography using SRAF, low-leak transistors fabricated by optimized SiON and S/D junction design, CoSi2, SRAM cell with acceptable operational margin, and full-NCS/duabdamascene Cu interconnects. It is emphasized that this technology is cost-effective.

SUPPRESSION OF TRANSIENT ENHANCED DIFFUSION BY LOCAL-OXIDATION-SILICON-INDUCED STRESS

We evaluated the transient enhanced diffusion (TED) of boron on two different local oxidation silicon (LOCOS) structures. Boron profiles were measured by secondary ion mass spectroscopy (SIMS) sputtering from the back surface of the wafers to eliminate any effects caused by uneven surfaces of the LOCOS structures. To evaluate the TED at the surface, we also measured the threshold voltage roll-off of n-type metal-oxide-semiconductor transistors. The TED of boron was suppressed for the LOCOS structure with a high mechanical stress.

Photo-excited dry cleaning for ULSI devices

The authors studied the reverse current in n/sup +/p junctions after photo-excited cleaning for samples fabricated by RIE. Silicon surfaces of a wafer contaminated during RIE were etched by photo-excited dry cleaning using chlorine, after which the unexpectedly large junction leakage current often occurring after wet cleaning alone was completely suppressed.<<ETX>>

Fabrication of twin transistors using sidewall masks for evaluating threshold voltage fluctuation

We propose a twin MOSFET fabrication technique to evaluate threshold voltage (Vt) fluctuations. Twin gates have been made using SiN sidewall masks that provide exactly the same gate lengths. From the difference in Vt between the twin transistors, we can evaluate the Vt fluctuation due not to a global variations across a wafer, but due to local variations. The standard deviation of the gate length difference between the twin transistors is smaller than 0.48 nm at a gate length of 95 nm.