Toshiro Nakanishi

Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

We demonstrated SONOS flash memory with a SiO/sub 2//High-k/SiO/sub 2/ structure based on a 2-bit/cell scheme. We evaluated three kinds of high-k dielectric films which were Si/sub 3/N/sub 4/, Al/sub 2/O/sub 3/ and HfO/sub 2/. Among these films, Al/sub 2/O/sub 3/ showed superior retention characteristics. The charge loss amount of Al/sub 2/O/sub 3/ at 150/spl deg/C is almost the same as that of Si/sub 3/N/sub 4/ at 25/spl deg/C. HfO/sub 2/ showed poor retention characteristics. In addition, we have found that each film has a different charge loss mechanism. We speculate that Si/sub 3/N/sub 4/ causes vertical charge migration, Al/sub 2/O/sub 3/ causes scarcely any leakage, and HfO/sub 2/ causes lateral charge migration. As a consequence, Al/sub 2/O/sub 3/ is very suitable for a charge trapping layer in multi-bit SONOS memory.

High-Density Layer at the SiO2/Si Interface Observed by Difference X-Ray Reflectivity

We have developed a high-accuracy difference X-ray reflectivity (DXR) method using intense synchrotron radiation for the evaluation of ultrathin thermal oxides on Si(100). By carefully analyzing DXR data for gate oxides with thicknesses of 40 A and 70 A grown at 800° C to 1000° C, the existence of a dense ( ~2.4 g/cm3), thin (~10 A) layer at the SiO2/Si interface has been revealed. The thickness of the interfacial layer decreases with increasing oxidation temperature. Oxides grown in O3 or HCl/O2 have a thinner interfacial layer compared to those grown in O2.

Degradation of metal‐oxide‐semiconductor devices caused by iron impurities on the silicon wafer surface

A reliable method of controlling iron impurities on the silicon wafer surface at low levels has been developed by using an iron‐contaminated HNO3 solution. Iron ions are thought to react with the silicon native oxide to form an Fe(III)‐O complex in proportion to the iron concentration in the solution. Using this method, we have quantitatively investigated the influence of iron impurities on metal‐oxide‐semiconductor device characteristics. The drastic degradation of generation lifetime, surface generation velocity, and dielectric breakdown strength of SiO2 have been observed above the surface iron concentration of 1×1012, 5×1012, and 1×1013 cm−2, respectively.

Thermal oxide growth at chemical vapor deposited SiO2/Si interface during annealing evaluated by difference x-ray reflectivity

The x-ray interference technique has been applied to evaluate the structural changes of high temperature grown chemical vapor deposited (CVD) SiO2 film under several post annealing conditions. In annealing above 800 °C in O2 ambient, a thermal oxide growth has been found at the CVD SiO2/Si interface, and its precise thicknesses have been determined. The estimated diffusion coefficient of the oxidant in CVD film was about three times larger compared to that of thermal oxide. A threshold voltage shift in the oxide was found to strongly correlate to the thickness of the thermal oxide rather than to thermal modifications of the CVD SiO2 itself.

New nonvolatile memory with charge-trapping sidewall

This letter reports on the development of a new nonvolatile memory with charge-trapping sidewalls using sub-0.1-/spl mu/m MOSFET technology. This memory has silicon nitride (SiN) sidewalls at both sides of the gate to store the charge. We have found that optimization of the p-n junction edge with the sidewall enables writing, reading, and erasing a 2-bit charge independently. The Vth window, which is the difference in the threshold voltage between forward and reverse read, was about 0.8 V with a gate length of 0.4 /spl mu/m. In addition, it is scalable to 40 nm of the gate length. This device is attractive not only from the prospects of future size reduction, but also its compatibility with CMOS process.

Ultraclean Technique for Silicon Wafer Surfaces with HNO3-HF Systems

We have developed a wafer cleaning technique called the slight etch (SE) using an HNO3 and trace HF mixture. A 30 nm surface removal by the SE reduces the surface Fe concentration by one tenth, compared to conventional RCA and all measured elements below a concentration of 1010 cm-2, without roughness degradation. The ultraclean surface results in a significant improvement in the C-t retention time and defect density of SiO2. Since the etch selectivity of silicon for the oxide is more than 10, this cleaning is also ideal for wafers with patterned oxides.

High-Accuracy X-ray Reflectivity Study of Native Oxide Formed in Chemical Treatment

High-accuracy X-ray reflectivity measurements using synchrotron radiation have been carried out to study native oxides formed during various chemical-cleaning processes on Si wafer. Clear differences in the density of native oxides between various chemical treatments were obtained from the normalized reflectivity for the first time. Native oxides formed by HCl and NH4OH solutions have a low density, in contrast to the oxides formed by H2SO4 solution and UV/O3 whose densities are close to that of thermal oxide. These results are closely related to the results of chemical studies and the etching characterization of native oxides.

Behavior of Fe Impurity during HCl Oxidation

Behavior of Fe impurity at the Si-SiO 2 interface of a metal-oxide-semiconductor (MOS) made through HCl oxidation was studied with electrical measurements and transmission electron microscopy. Fe impurity was introduced in silicon wafers by ion implantation to the doses of 1.0 x 10 15 and 1.0 x 10 14 cm -2 . The wafers were then oxidized in HCl/O 2 ambient. The Fe impurity either nucleated (1.0 x 10 15 cm -2 ) to precipitates in the Si substrate near the Si-SiO 2 interface or scattered uniformly in the SiO 2 (1.0 x 10 15 and 1.0 x 10 14 cm -2 ). The precipitates were identified as metallic α-FeSi 2 or semimetallic FeSi. The precipitate is supposed to form a weak spot in the silicon oxide, where the electric field is strengthened ; however, the dielectric effect of uniformly scattered Fe impurity in the SiO 2 film is relatively small. Fe precipitates were gradually included into the SiO 2 film and finally dissolved during HCl oxidation. As a result, Fe impurity was scattered in the middle area of the SiO 2 film. The gettering ability of HCl oxidation is attributed to its enhancement of dissolution of Fe-silicides in the SiO 2 film.

Structural relaxation of SiO2/Si interfacial layer during annealing

Abstract We have studied the structural evolution of the high density interfacial layer around 10 A thick in 40 A thermal oxide observed by difference X-ray reflectivity (DXR) techniques during thermal annealing. Effects of interfacial stress are evaluated by grazing incidence X-ray diffraction. As the annealing proceeds, density of the interfacial layer decreased and got close to the value of the upper SiO 2 layer after 2 h of annealing in Ar at 800°C. At the same time, a slight increase in the thickness of the interfacial layer and the flattening of the Si interface are observed. These results indicate that during annealing, both the structural relaxation of oxide in the direction normal to the interface and an atomic rearrangement at the Si interface proceeds. Elastic deformation by stress can not be the dominant origin of the density change. The observed decrease of the interface state density D it along annealing may be linked to the decrease of structural defects accompanied with the structural relaxation at the interface.

Identification of MOS Gate Dielectric Breakdown Spot Using High Selectivity Cl Radical Etching Technique

We have developed a simple method for identifying dielectric breakdown spots in gate oxides by using high selectivity Cl radical etching. This method is based on the phenomenon that Cl radicals do not penetrate SiO 2 . They can etch the Si substrate through the breakdown spot which acts as the etching path, namely, the current leakage path. During over-etching of the poly-Si gate electrode, a cavelike etched region in the Si substrate appeared under the breakdown spot of the gate oxide. This breakdown spot could be found by focusing the optics on the gate oxide located at a center on the etched region. We confirmed the local structure of the gate oxide which converted to crystallized Si due to intrinsic dielectric breakdown using transmission electron microscopy and energy dispersive x-ray spectroscopy. Cl radicals can etch the breakdown spot such as part of the crystallized Si in the gate oxide produced by intrinsic dielectric breakdown, and then etch a Si substrate under the breakdown spot.