Masaki Saito

Mobility improvement for 45nm node by combination of optimized stress and channel orientation design

Performance improvement of CMOSFET by adopting <100>-channel direction with high tensile stress gate capping layer (GC liner-SiN) was demonstrated. For pMOSFET, higher hole mobility of <100>-channel and lesser short channel effect (SCE) results in 20% improvement of I/sub on/. In addition, this improvement was not sensitive to local uniaxial strain. For nMOSFET, similar to <110>-channel, 10% improvement of I/sub on/ is realized in <100>-channel with high tensile stress gate capping layer. Thus, this technology can improve the performance of nMOSFET and pMOSFET without introducing specific additional processes for nMOSFET and pMOSFET.

Efficient 2 nd and 4 th harmonic generation of a single-frequency, continuous-wave fiber amplifier

We demonstrate efficient cavity-enhanced second and fourth harmonic generation of an air-cooled, continuous-wave (cw), single-frequency 1064 nm fiber-amplifier system. The second harmonic generator achieves up to 88% total external conversion efficiency, generating more than 20-W power at 532 nm wavelength in a diffraction-limited beam (M(2) < 1.05). The nonlinear medium is a critically phase-matched, 20-mm long, anti-reflection (AR) coated LBO crystal operated at 25 degrees C. The fourth harmonic generator is based on an AR-coated, Czochralski-grown beta-BaB(2)O(4) (BBO) crystal optimized for low loss and high damage threshold. Up to 12.2 W of 266-nm deep-UV (DUV) output is obtained using a 6-mm long critically phase-matched BBO operated at 40 degrees C. This power level is more than two times higher than previously reported for cw 266-nm generation. The total external conversion efficiency from the fundamental at 1064 nm to the fourth harmonic at 266 nm is >50%.

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

Novel channel-stress enhancement technology on damascene gate process with eSiGe S/D for pFET is demonstrated. It is found for the first time that the damascene gate process featured by the dummy gate removal is more effective in increasing channel strain than the gate-1st process as an embedded SiGe stressor technique is used. Furthermore, an additional channel recess related to the damascene process is shown to enhance channel strain, resulting in a 14% Ion improvement at Ioff = 100 nA/um. We propose combining these strain techniques with high-k/metal gate stacks for low-power and high-performance pFETs.

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

Extreme high-performance n- and pFETs are achieved as 1300 and 1000 uA/um at Ioff = 100 nA/um and Vdd = 1.0 V, respectively, by applying newly proposed booster technologies. The combination of top-cut dual-stress liners and damascene gate remarkably enhances channel stress especially for shorter gate lengths. High-Ion pFETs with compressive stress liners and embedded SiGe source/drain are performed by using ALD-TiN/HfO2 damascene gate stacks with Tinv = 1.4 nm on (100) substrates. On the other hand, nFETs with tensile stress liners are obtained by using HfSix/HfO2 damascene gate stacks with Tinv =1.4 nm.

High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

We have developed a dual metal gate CMOS technology with HfSi_x for nMOS and Ru for pMOS on HfO₂ gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to T_inv of 1.7 nm and symmetrical low V_t equivalent to poly-Si/SiO₂. As a result, high drive currents of 780 muA/mum and 265 muA/mum at I_off = 1 nA/mum are achieved for V_dd = 1.0 V in L_g = 60 nm nMOS and pMOS, respectively We have applied the mobility enhancement technology to the Ru/HfO₂ pMOS by utilizing (110)-substrate. As a result, an excellent drive current of 400 muA/mum (151% improvement over (100)-p⁺poly-Si/SiO₂) is achieved

Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule (190 nm) in 45 nm technology node.

High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

This paper describes the fabrication and performance of CMOS transistors featuring flash lamp annealing (FLA) for 45 nm node. We show, for the first time, applying FLA prior to spike RTA as S/D annealing is effective to enhance the channel stress in PFET with epitaxially grown SiGe (eSiGe) S/D. In NFET, FLA recovers the damaged layer in S/D extension caused by implantation and suppresses the transient enhanced diffusion (TED). These improvements result in 11% and 8% higher saturation drive current, and IDSAT=750muA/mum and 1160muA/mum for IOFF=100 nAmum at Vdd=lV in PFET and NFET, respectively. We also report the pattern density dependence of performance gain from FLA technique.

High Performance pMOSFET with ALD-TiN/HfO2 Gate Stack on (110) Substrate by Low Temperature Process

We have developed a high performance pMOSFET with ALD-TiN/HfO2 gate stacks on (110) substrate using gate last process at low temperature. High work function and low gate leakage current are obtained. An extremely high mobility equivalent to P+poly-Si/SiO2 on (110) substrate (171 cm2/Vs at 0.5 MV/cm) is achieved with ALD-TiN/HfO2 on (110) substrate in the thinner Tinv region of 1.7 nm. Vth roll-off characteristics are well controlled down to 50 nm. A high drive current of 380 uA/um at I off = 1 uA/um is achieved at Vdd = 1.0 V. The drive current of ALD-TiN/HfO2 gate stack on (110) substrate is improved 1.4 times compared with (100) substrate and 2.4 times compared with P+poly-Si/SiO2 on (100) substrate