Masanobu Kasuga

Growth of p-type Zinc Oxide Films by Chemical Vapor Deposition

The growth of p-type ZnO film was realized for the first time by the simultaneous addition of NH3 in carrier hydrogen and excess Zn in source ZnO powder. The resistivity was typically 100 Ωcm. A model showing nitrogen incorporation suggests the possibility of realizing p-type ZnO film of low resistivity by optimizing thermal annealing.

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Ultralow on-resistance silicon carbide static induction transistors with buried gate structures (SiC-BGSITs) have been successfully developed through innovative fabrication process. A submicrometer buried p⁺ gate structure was fabricated by the combination of submicrometer trench dry etching and epitaxial growth on a trench structure. The breakdown voltage V_BR and specific on-resistance R_onS of the fabricated SiC-BGSIT were 700 V at a gate voltage V_G=-12V, and 1.0 mOmegamiddotcm² at a current density J_D=200A/cm² and V_G=2.5V, respectively. This R_onS is the lowest on-resistance for ~600 V class power switching devices, including other SiC devices and GaN HEMTs

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A novel rectifier concept based on bipolar-mode static induction transistor (BSIT) operation is proposed. A numerical simulation has revealed that the turn-on mechanism of this rectifier, owing to a combination of static induction effects and minority carrier injection, can make its forward-voltage drop and reverse recovery time smaller than those of the conventional p-i-n rectifier. As an example of the design methods, the simulation has clarified the effects of decreasing the doping concentration in the channel between p/sup +/ regions on improvement in the tradeoff between a forward voltage drop and leakage current.<<ETX>>

Buried Gate SiC-SIT (SiC-BGSIT)

C-oriented ZnO epitaxial thin films were prepared on sapphire substrates by atmospheric-pressure metal organic chemical vapor deposition using diethyl zinc and water vapor as precursors. In-plane twins observed in ZnO films on sapphire (0001) substrates were reduced markedly by the use of (1120) substrates owing to a coincident-site lattice match and geometrical fitting. An extinction of peak splitting in the ?/2? scan and a reduction in full width at half maximum in rocking curves were also observed. In the case of the sapphire (0001) substrates, the rotational domains of the ZnO films were reduced by air-annealing of the substrates. It seems essential that the sapphire (0001) topmost surface be terminated by a single Al layer to eliminate the rotational domains.

Rectifier characteristics based on bipolar-mode SIT operation

A novel high-power rectifier using the BSIT (Bipolar mode Static Induction Transistor) operation has been demonstrated. In order to improve the reverse blocking capability of this diode, an ion implanted P-type channel structure is introduced. Device simulations have revealed that, as the tradeoff relationships between reverse blocking voltage, forward voltage drop, and reverse recovery time are considered, there exists an optimum set of the channel dosage and the channel width.

Effects of Sapphire Substrate Preparation on ZnO Epitaxial Growth by Atmospheric-Pressure Metal Organic Chemical Vapor Deposition

A novel low loss diode with junction grids has been proposed. Numerical simulations reveal that, for this diode, designing a submicron grid width improves the tradeoff characteristics between the forward voltage drop and the leakage current, leading to characteristics superior to those of the Schottky barrier diode. The introduction of a lateral silicon-on-insulator (SOI) structure into the proposed diode is attractive for achieving such a small grid width. The simulation also demonstrates design methods for channel doping and thickness of the buried oxide layer in the SOI diode.

High-power rectifier using the BSIT operation

Silicon carbide static induction transistors with submicron buried p+ gate (SiC-BGSITs) have been successfully developed through innovative fabrication process. A submicron buried p+ gate structure was fabricated by the combination of submicron trench dry etching and epitaxial growth process on a trench structure. As the device performance is mainly determined by the width of the p+ gate region and the spacing between two adjacent p+ gate regions, corresponding to the width of n- channel, we have optimized these parameters carefully using a device simulator. The breakdown voltage VBR and specific on-resistance RonS of the fabricated BGSIT were 700 V at a gate voltage VG = –12 V and 1.01 m/·cm2 at VG = 2.5 V and a drain current density JD = 200 A/cm2, respectively. This RonS is the lowest on-resistance for ~ 600V class power switching devices, including other wide-bandgap materials such as GaN.

Application of a Junction Field Effect Transistor Structure to a Low Loss Diode

A tunnel metal–insulator–semiconductor (MIS) solar cell with an n-type substrate is analyzed by a one-dimensional numerical simulation. The degradation of the maximum output power with the increase in interfacial layer thickness is caused by minority carrier injection into the quasi-neutral region with both optically induced forward bias and applied forward bias. This prevents the photogenerated minority carriers from diffusing from the quasi-neutral region to the depletion region edge. The resultant shortage of minority carrier supply on the semiconductor surface decreases the current extracted from the semiconductor. The obtained concave upward output characteristics under illumination, which are the main reason for the significant degradation of the fill factor, strongly depend on the saturation of the amount of injected minority carriers. The simulation also reveals that, when either interface state density or metal work function is increased, the above degradation can be improved.

Fabrication of 700V SiC-SIT with Ultra-Low On-Resistance of 1.01mΩ•cm2

Tunnel metal-insulator-semiconductor (MIS) SnO2–nSi solar cells were made by oxidizing (100) and (111) Si substrates at various oxidation temperatures and times, and by spray-depositing SnO2 to the surface. Open-circuit voltage V oc decreases with increasing oxidation temperature, and the cells made on (100) Si have higher V oc than those on (111) Si which were made under the same oxidation conditions. V oc is related to the n-factor and effective barrier height. The n-factor increases linearly with increase of the density of surface states D ss, while the effective barrier height decreases slowly with increase of D ss. For the improvement of V oc, it is effective to increase D ss. Experimental results support the theoretical prediction. When the oxidation temperature decreases, D ss increases, which results in an increase of the n-factor and V oc. The (100) solar cell has a higher V oc than the (111) cell because it has a higher D ss.

Analysis of output power degradation for tunnel metal-insulator-semiconductor solar cell

The authors propose a novel rectifier based on bipolar-mode static induction transistor (BSIT) operation. A numerical simulation has revealed that, this rectifier, which operates with a combination of static induction effects and minority carrier injection during forward conduction, exhibits a forward-voltage drop and a reverse recovery time that are smaller than those of the conventional p-i-n rectifiers, and without causing excessive leakage current. It is also shown that, at temperatures below 400 K, the steady state power dissipation for the rectifier using BSIT operation is superior to that for the p-i-n rectifiers and the Schottky rectifiers.