Koji Yano

Growth of p-type Zinc Oxide Films by Chemical Vapor Deposition

The growth of p-type ZnO film was realized for the first time by the simultaneous addition of NH3 in carrier hydrogen and excess Zn in source ZnO powder. The resistivity was typically 100 Ωcm. A model showing nitrogen incorporation suggests the possibility of realizing p-type ZnO film of low resistivity by optimizing thermal annealing.

Short-Circuit Capability of SiC Buried-Gate Static Induction Transistors: Basic Mechanism and Impacts of Channel Width on Short-Circuit Performance

Fundamental short-circuit operations of silicon carbide static induction transistors with buried-gate structures (BGSITs) were experimentally clarified, with subsequent device simulations. The impacts of channel width and source length on short-circuit capabilities were investigated. In particular, a design concept of the channel width was proposed to improve the short-circuit energy without a serious increase in on-resistance. The maximum short-circuit capability of the fabricated BGSITs was 18 J/cm2 at room temperature, which shows excellent performance compared with that of conventional Si insulated-gate bipolar transistors.

Shape Transformation of 4H-SiC Microtrenches by Hydrogen Annealing

This study investigates the shape transformation of 4H-SiC microtrenches that occurs during high-temperature hydrogen annealing, which is used to improve growth on such prepared substrates. The trenches have micron-sized widths and depths and were annealed in hydrogen ambient at temperatures of 1400–1600 °C for 30–3600 s. After hydrogen annealing, cross-sectional images of the samples were obtained by scanning electron microscopy (SEM). These SEM images reveal that the top and bottom trench corners become rounded during hydrogen annealing. The top trench corners become rounded by an etching reaction, whereas the bottom trench corners become rounded as a result of a regrowth phenomenon that involves the transportation of atoms. This study analyzes the mechanism of these transformations in terms of Mullins continuum model. The results suggest that the evaporation–condensation process is dominant in the case of SiC annealing.

Application of a Junction Field Effect Transistor Structure to a Low Loss Diode

A novel low loss diode with junction grids has been proposed. Numerical simulations reveal that, for this diode, designing a submicron grid width improves the tradeoff characteristics between the forward voltage drop and the leakage current, leading to characteristics superior to those of the Schottky barrier diode. The introduction of a lateral silicon-on-insulator (SOI) structure into the proposed diode is attractive for achieving such a small grid width. The simulation also demonstrates design methods for channel doping and thickness of the buried oxide layer in the SOI diode.

SiC power devices for HEV/EV and a novel SiC vertical JFET

We propose a novel SiC VJFET with low feedback capacitance Crss. A key feature of the proposed VJFET is the p+ screen grid inserted between gate and drain electrode. The screen grid effectively reduces the Crss by about 80% compared to a conventional VJFET. The lowest total power dissipation among existing SiC power devices can be achieved by the low Crss. This new VJFET can be a promising candidate for a high-speed and low-loss SiC power device.

Evaluation of Refilled Channel Regions in 4H-SiC Buried Gate Static Induction Transistors

We evaluated the crystalline quality of the channel region in silicon carbide buried gate static induction transistors (SiC-BGSITs) by transmission electron microscopy (TEM) and scanning spreading resistance microscopy (SSRM). TEM observations revealed that no crystalline defects were generated in the channel region of SiC-BGSITs during epitaxial regrowth in trenches. The SSRM result indicated that the refilled channel region had a spreading resistance distribution of about ten times due to a high noise resulting from contact resistance. This noise was so high that we could not detect carrier density distributions from SSRM signals. However, on the basis of the leakage current and blocking characteristics of the SiC-BGSITs, we confirmed that there was no serious carrier density distribution that affected the device operation in the channel region.

Improvement of open circuit voltage of SnO2-nSi solar cells

Tunnel metal-insulator-semiconductor (MIS) SnO2–nSi solar cells were made by oxidizing (100) and (111) Si substrates at various oxidation temperatures and times, and by spray-depositing SnO2 to the surface. Open-circuit voltage V oc decreases with increasing oxidation temperature, and the cells made on (100) Si have higher V oc than those on (111) Si which were made under the same oxidation conditions. V oc is related to the n-factor and effective barrier height. The n-factor increases linearly with increase of the density of surface states D ss, while the effective barrier height decreases slowly with increase of D ss. For the improvement of V oc, it is effective to increase D ss. Experimental results support the theoretical prediction. When the oxidation temperature decreases, D ss increases, which results in an increase of the n-factor and V oc. The (100) solar cell has a higher V oc than the (111) cell because it has a higher D ss.

An Average Input Current Sensing Method of LLC Resonant Converters for Automatic Burst Mode Control

Burst mode control techniques have been studied for LLC resonant dc–dc converters to improve power conversion efficiencies at light load conditions. However, there are not many studies about how to detect the load conditions at burst mode not even at normal mode, at the primary side of LLC resonant dc–dc converters. In this paper, we propose and implement a lossless load detection technique for normal and burst modes by a novel average input current sensing method at the primary side of LLC resonant converters. Detailed theoretical analysis at normal and burst modes is presented and a load detection circuit is proposed with the consideration of integrated circuits. To verify the analysis, an LLC resonant offline converter with 400 V input and 16 V/10 A output is simulated using PSIM and a prototype board is built. The experimental results show that the proposed load detection technique is valid and practical. As a result, an automatic burst mode control for LLC resonant converters at light load conditions is realized with the proposed average input current sensing method.

Experimental demonstration of SiC screen grid vertical JFET (SiC-SGVJFET) having a ultra-low Crss

We have implemented a novel SiC power JFET having a ultra-low feedback capacitance Crss and the voltage rating of 1200V, which is called the screen grid vertical JFET (SGVJFET). Capacitance-voltage tests have made it clear that the introduction of the screen grid drastically reduces the Crss. Impacts of the spacing between the adjacent screen grids on the static and switching characteristics have been investigated.

A novel rectifier based on bipolar-mode SIT structure

The authors propose a novel rectifier based on bipolar-mode static induction transistor (BSIT) operation. A numerical simulation has revealed that, this rectifier, which operates with a combination of static induction effects and minority carrier injection during forward conduction, exhibits a forward-voltage drop and a reverse recovery time that are smaller than those of the conventional p-i-n rectifiers, and without causing excessive leakage current. It is also shown that, at temperatures below 400 K, the steady state power dissipation for the rectifier using BSIT operation is superior to that for the p-i-n rectifiers and the Schottky rectifiers.