Akio Takatsuka

700-V 1.0-

Ultralow on-resistance silicon carbide static induction transistors with buried gate structures (SiC-BGSITs) have been successfully developed through innovative fabrication process. A submicrometer buried p⁺ gate structure was fabricated by the combination of submicrometer trench dry etching and epitaxial growth on a trench structure. The breakdown voltage V_BR and specific on-resistance R_onS of the fabricated SiC-BGSIT were 700 V at a gate voltage V_G=-12V, and 1.0 mOmegamiddotcm² at a current density J_D=200A/cm² and V_G=2.5V, respectively. This R_onS is the lowest on-resistance for ~600 V class power switching devices, including other SiC devices and GaN HEMTs

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UMOSFET is theoretically suitable to decrease the on-resistance of the MOSFET. In this study, in order to determine the cell structure of the SiC UMOSFET with extremely low on-resistance, influences of the orientation of the trench and the off-angle of the wafer on the MOS properties are investigated. The channel resistance, gate I-V curves and instability of threshold voltage are superior on the {11-20} planes as compared with other planes. On the vicinal off wafer, influence of the off-angle disappears and the properties on the equivalent planes are almost the same. The obtained results indicate that the extremely low on-resistance with the high stability and high reliability is possible in the SiC UMOSFET by the hexagonal cell composed of the six {11-20} planes on the vicinal off wafer, and actually an extremely low channel resistance was demonstrated on the hexagonal UMOSFET with the six {11-20} planes on the vicinal off wafer.

Buried Gate SiC-SIT (SiC-BGSIT)

Fundamental short-circuit operations of silicon carbide static induction transistors with buried-gate structures (BGSITs) were experimentally clarified, with subsequent device simulations. The impacts of channel width and source length on short-circuit capabilities were investigated. In particular, a design concept of the channel width was proposed to improve the short-circuit energy without a serious increase in on-resistance. The maximum short-circuit capability of the fabricated BGSITs was 18 J/cm2 at room temperature, which shows excellent performance compared with that of conventional Si insulated-gate bipolar transistors.

Isotropic Channel Mobility in UMOSFETs on 4H-SiC C-Face with Vicinal Off-Angle

We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.

Short-Circuit Capability of SiC Buried-Gate Static Induction Transistors: Basic Mechanism and Impacts of Channel Width on Short-Circuit Performance

In this study, we evaluated the radiation hardness of SiC Buried Gate Static Induction Transistors (SiC-BGSITs) and Si-based switching devices up to the absorbed dose of 10 MGy(SiO2). The on-voltage Von of Si-IGBT degraded excessively at the early stage of the irradiation (>~0.1 MGy(SiO2)) due to the bulk damage produced by Compton electrons like the gain degradation in Si bipolar transistors. The threshold voltage Vth of Si-MOSFET was very sensitive against the radiation due to the competing mechanism between the generation of the hole traps in the gate SiO2 and the SiO2/Si interface states. Moreover, the breakdown voltage VBR and leak current Ileak of MOSFET degraded significantly against the absorbed dose. While, the electrical properties of SiC-BGSIT was very stable even after the irradiation of 10 MGy(SiO2).

1270V, 1.21mΩ·cm2 SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.

Radiation Hardness Evaluation of SiC-BGSIT

Ultra low on-resistance silicon carbide static induction transistors with buried gate structures (SiC-BGSITs) have been successfully developed. A submicron buried p⁺ gate structure was fabricated by the combination of submicron trench dry etching and epitaxial growth on a trench structure. A drain current I_DS reached 8 A at a drain voltage V_DS = 1 V, corresponding to a specific on-resistance R_onS of 1.1 mOmegamiddotcm² at a current density J_D = 200 A/cm², in the BGSIT with the channel width W_ch of 0.9 mum. A breakdown voltage V_BR was ~700 V at a negative gate bias V_G = -12 V. A clear saturation I_DS-V_DS characteristic and slightly high R_onS (1.4 mOmegamiddotcm²) were observed in the BGSIT with narrow Wch of 0.7 mum. R_onS increased in proportion to T^2,3 in any channel width due to enhanced phonon scattering.

980 V, 33A Normally-Off 4H-SiC Buried Gate Static Induction Transistors

Silicon carbide static induction transistors with submicron buried p+ gate (SiC-BGSITs) have been successfully developed through innovative fabrication process. A submicron buried p+ gate structure was fabricated by the combination of submicron trench dry etching and epitaxial growth process on a trench structure. As the device performance is mainly determined by the width of the p+ gate region and the spacing between two adjacent p+ gate regions, corresponding to the width of n- channel, we have optimized these parameters carefully using a device simulator. The breakdown voltage VBR and specific on-resistance RonS of the fabricated BGSIT were 700 V at a gate voltage VG = –12 V and 1.01 m/·cm2 at VG = 2.5 V and a drain current density JD = 200 A/cm2, respectively. This RonS is the lowest on-resistance for ~ 600V class power switching devices, including other wide-bandgap materials such as GaN.

Buried Gate Static Induction Transistors in 4H-SiC (SiC-BGSITs) with Ultra Low On-Resistance

In this paper, we introduce silicon carbide (SiC) buried gate static induction transistors (BGSITs) which can be applied for circuit breakers in DC distribution systems. SiC-BGSITs have excellent electrical properties such as low on-resistance, first switching speed and robustness. These properties are indispensable for the realization of semiconductor circuit breakers in DC distribution systems and cannot be achieved by any other semiconductor materials.

Fabrication of 700V SiC-SIT with Ultra-Low On-Resistance of 1.01mΩ•cm2

400V DC distribution systems have attracted much attention recently as the next generation power distribution systems for data centers. For the reliability of these networks, the development of high speed DC circuit breaker for overcurrent protection is essential. In existing research, semiconductor DC circuit breakers using silicon carbide static induction transistors (SiC-SITs) show to be a promising candidate as these high speed DC circuit breakers. In this case, the overvoltage generated across the drain-source terminals of the SiC-SIT device during the turn-off process is highly dependent on the applied turn-off gate-source voltage and the variation in characteristic of the devices. In this paper, the active voltage control method is proposed to suppress the overvoltage to a predetermined range even when variation in characteristic of the devices exists. The effectiveness of the proposed method is demonstrated by experiments.