Masao Ikekawa

Fast and accurate motion estimation algorithm by adaptive search range and shape selection

The paper presents a fast and accurate motion estimation algorithm. To obtain accurate motion vectors while minimizing computational complexity, we adjust the search range for each frame and each block to suit the motion level of the video. An appropriate search range for each frame is determined on the basis of motion vectors and prediction errors obtained for the previous frame. At each block, the search range is determined on the basis of the search range of its frame and of the motion vector values of all adjacent blocks for which those values have already been obtained. With our algorithm, since narrow search ranges are chosen for areas in which little motion occurs, computational complexity can be reduced without degrading estimation accuracy. Since wide search ranges are chosen for areas of significant motion, good video-quality encoding can be maintained. In the encoding of an SDTV size video, the addition of range adjustment results in a reduction in the computational complexity of motion estimation of roughly 65%, while maintaining the same video quality.

Parallel variable length decoding with inverse quantization for software MPEG-2 decoders

Fast methods of variable length decoding (VLD) and inverse quantization (IQ) are proposed for software MPEG-2 video decoders. In these methods, microprocessors with SIMD type instructions execute VLD and IQ efficiently. The use of memory-efficient tables enables decoding multiple variable length codewords concurrently. In addition, the concurrently decoded data are inversely quantized in parallel by making full use of SIMD type instructions. Combining these two methods achieves 27-32% reduction of the clock cycles for VLD and IQ compared to a conventional method. The proposed methods are particularly effective for high bitrate streams.

Extended instructions for the AES cryptography and their efficient implementation

In this paper, extended instructions for the advanced encryption standard (AES) cryptography acceleration in embedded processors and efficient implementation of these instructions are presented. These AES instructions generate four elements in single-instruction, multiple-data format from each input of an AES state. The instruction count for 128-bit key AES encryption can be reduced from 688 to 340 per 128-bit block by using the proposed AES instructions. The execution unit for the AES instructions can be implemented efficiently with a single 2-Kbit table and four small multipliers. The capacity of the table has been reduced to 1/32, compared to that of a conventional fast software algorithm. The AES instructions enable embedded processors for low-cost network equipment to have cryptographic capability with minimal modification.

Fast 2D IDCT implementation with multimedia instructions for a software MPEG2 decoder

This paper presents an implementation of a fast two-dimensional inverse discrete cosine transform (IDCT) with multimedia instructions for a software MPEG-2 decoder. IDCT algorithms for sparse blocks which eliminate the calculation for zero coefficients are realized by using multimedia instructions. To reduce the cycle count for IDCT, an adaptive control method for these IDCT algorithms, based on the bit rate and picture type, is proposed and its performance is described. In the implementation of a software MPEG-2 decoder, the execution time for IDCT is reduced to 10% by using MMX instructions from the original C program. Moreover, using the proposed adaptive control, it can further be reduced to 76%.

A low-power programmable DSP core architecture for 3G mobile terminals

We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless communications at 384 k bit/sec with a power consumption of approximately 50 mW. This paper presents an overview of both the DSP core architecture and a DSP instruction set, and it also gives some application benchmarks.

High-quality and processor-efficient implementation of an MPEG-2 AAC encoder

Presents MPEG-2 AAC LC Profile encoder software for an Intel Pentium III processor. Modified discrete cosine transform (MDCT) and quantization processing are accelerated by the use of SIMD instructions. Psycho-acoustic analysis in the MDCT domain makes the use of FFTs unnecessary. Better sound quality is provided by greater efficiency in quantization processing and Huffman coding. All of this results in high-quality and processor-efficient implementation of an MPEG-2 AAC encoder. Sound quality achieved at 96 kbps/stereo is significantly better than that of MP3 at the same bitrate. The encoder works 13 times faster than realtime for stereo encoding on an 800MHz Pentium III processor.

A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications

A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the processors performance with that of dedicated hardware. Despite its flexibility, the processor achieves a computational density of 57% that of dedicated hardware.

Real-time software MPEG-1 video decoder design for low-cost, low-power applications

This paper presents a real-time MPEC-1 video decoder implemented in software on a DSP-enhanced, 160-mW, 100-MHz, 32-bit microprocessor. The processors DSP-oriented instructions improves the performance of generic DSP operations such as the inverse discrete cosine transform, while fast software algorithms that perform parallel operation on packed-pixel data are developed for processes unique to video decoding such as motion compensation. Furthermore, to reduce the clock count as well as the instruction count, load/store scheduling and cache miss reduction are performed. In total, the processor can achieve 30 frames/sec MPEC-1 video decoding at a cost and power dissipation (160 mW) comparable to dedicated LSIs.

Code positioning to reduce instruction cache misses in signal processing applications on multimedia RISC processors

Real-time operation of signal processing applications on multimedia RISC processors is often limited by high instruction cache miss rates of direct-mapped caches. In this paper, a heuristic approach is presented which reduces high instruction cache miss rates in direct-mapped caches by code positioning. The proposed algorithm rearranges functions in memory based on trace data so as to minimize cache line conflicts. Moreover, a new method to extract potential cache misses from trace data is introduced which enables accurate cache behavior analysis and greatly enhances code positioning efficiency. Application of code positioning to an MPEG-1 video decoder implementation on the V830 multimedia RISC processor reduced instruction cache refill cycles by 66-98%. The proposed code positioning algorithm does not require hardware modifications; it can easily be integrated in an object linker to automate the optimization process.

Effective channel coding combined with low bit-rate speech coding for digital cellular system

A channel coding method for a half-rate speech codec is proposed. This method includes new error control techniques that effectively integrates a speech codec with a channel codec. It utilizes bit swelling technique for an efficient unequal error protection. Highly significant bits are swollen and combined with other significant bits. Combined bits are coded with a convolutional code. In addition, the Viterbi decoder employs temporal correlation in encoded speech data as well ail the redundancy of convolutional code, to improve its decoding performance. The paper shows the error correction ability for this method is higher than that for a conventional method. A subjective test shows that the speech quality for a half-rate speech codec combined with the proposed channel codec is considerably better than that for the full-rate VSELP codec on a fading channel.<<ETX>>