Takahiro Kumura

VLIW DSP for mobile applications

We have developed a new digital signal processor (DSP) core for handheld terminals, the SPXK5 performance and flexibility, is compatible with high-level languages, and its architecture features low-power consumption. We describe the SPXK5 architecture and its performance in DSP applications. We also consider the question of application-specific enhancements. Such architecture enhancements as add-compare-select instructions or coprocessors for the Viterbi (1995) decoding algorithm are employed in some programmable DSPs, and for video codecs, other architectures include either single-instruction multiple-data (SIMD) instructions or media coprocessors. While such application-specific enhancements are valuable when their applications are actually in use, they do nothing to enhance the performance of other applications, and the more they are added, the greater the increase in chip size and energy requirements. In other words, for handheld terminals, such enhancements need to be chosen in a careful and balanced way. We have done this in developing the SPXK5, in which a wide range of signal processing algorithms are efficiently implemented.

Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors

This paper proposes a method of software development tool generation suitable for instruction set extension of existing embedded processors. The key idea in the proposed method is to enhance a base processors toolchain by adding plugins, which are software components that handle additional instructions and registers. The proposed method can generate a compiler, assembler, disassembler, and instruction set simulator. Generated compilers with the plugins provide intrinsic functions that are translated directly into the new instructions. To demonstrate that the proposed method works effectively, this paper presents an experimental result of the proposed method in the study of adding SIMD instructions to the embedded microprocessor V850. In the experiment, by using intrinsic functions, the compiler generated good code with only 7% increase in the number of instructions against the hand-optimized assembly codes.

Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core

This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.

Multimedia signal processor for mobile applications

This paper describes an efficient architecture enhancement for video codec on a new-generation, general-purpose digital signal processor (DSP) core called SPXK5 developed for handheld devices. With high performance features of SPXK5s base architecture, an MPEG-4 video codec can be implemented efficiently. In addition, only a few SIMD type instructions effectively accelerate MPEG-4 video codec implementation by 20% with only 2.5% hardware increase. By reducing cycle count, the DSPs power consumption can be reduced. Both video and speech codec for 3G mobile service at 384kbps can be realized with a power consumption of less than 50mW.