Tomoyoshi Kobori

A 335Mb/s 3.9mm 2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates

In current and future wireless standards, such as WiMAX, 3GPP-LTE or LTE-Advanced, receiver terminals have to support numerous operating modes for each protocol [1], as well as sophisticated transmission techniques, especially enhanced MIMO detection and iterative forward error correction (FEC). MIMO detection and FEC belong to the most computationally complex parts of the receiver-side baseband signal processing chain. Implementations thereof must have low power consumption, but also be able to interact in a flexible and efficient way in the detection-decoding engine, while at the same time not compromising on the challenging throughput and flexibility requirements associated with 4G standards. In this paper, we present a chip implementation of a MIMO sphere detector combined with a flexible FEC engine, realizing a detection-decoding engine in silicon capable of satisfying 4G requirements with a data rate of 335Mb/s.

A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications

A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the processors performance with that of dedicated hardware. Despite its flexibility, the processor achieves a computational density of 57% that of dedicated hardware.

A ”multi-user” approach towards a channel decoder for convolutional, turbo and LDPC codes

In this paper we present the concept of a high-throughput multi-mode channel decoder architecture that consists of a tightly coupled array of independently programmable processing cores. Every core is capable of decoding low-density parity-check (LDPC), convolutional turbo (CTC) and con-volutional codes (CC) either independently or jointly with other cores. This approach allows parallel handling of several separate decoding processes in one decoder engine as well as performing a single high-throughput decoding, opening up a new level of flexibility for channel decoding. The multi-mode decoder core as well as the multi-core approach are explained and simulation results presented. A case study of the proposed architecture was implemented in a 65nm-process using an area of 0.44 mm2. At 200 MHz, throughputs of up to 86 Mbps could be reached.

Combining LDPC, turbo and Viterbi decoders: Benefits and costs

In this paper we present a detailed analysis into the benefits and costs of merging decoders for different channel code types such as convolutional, turbo and LDPC codes. An ASIP (application-specific instruction set processor)-based framework for multi-code forward error correction (FEC) architectures is applied to implement three dedicated decoders for convolutional, turbo and LDPC codes respectively as well as one decoder capable of decoding all three. Synthesis results and performance estimations for all architectures are presented and used to draw a clear and fair comparison between single-mode and multi-mode decoders.