Masao Okihara

Radiation Resistance of SOI Pixel Devices Fabricated With OKI 0.15

Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32×32 pixels each with 20 μm square were irradiated with ⁶⁰Co γ’s up to 0.60 MGy and with 70-MeV protons up to 1.3×10¹⁶ 1-MeV n<inf>eq</inf>/cm². The performance characterization was made on the electronics part and as a general detector from the response to RESET signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation using transistor test structures was separately carried out with covering a wider range of radiation level (0.12 kGy to 5.1 MGy) with ⁶⁰Co γ’s.Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32times32 matrix with 20 mum times 20 mum pixels were irradiated with 60Co gammas up to 0.60 MGy and with 70-MeV protons up to 9.3times10 60Co p/cm2. The performance characterization was made on the electronics part and as a photon detector from the response to reset signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation of the characteristics changes in the transistors was separately carried out using transistor test structures to which a wider range of irradiation, from 0.12 kGy to 5.1 MGy, was made with 60Co gammas.

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We have been developing the 0.2 μm fully-depleted Silicon On Insulator (SOl) CMOS technology for monolithic pixel detectors. In order to improve the sensors sensitivity, 8 inch FZ wafer is introduced for handle substrate in SO! wafer. Stitching technology is also developed to get large detector chip area. Furthermore, nested well structure for the p-n junction and double-SOI structure are investigating for reducing the radiation damage and crosstalk between electrical circuitry in top silicon layer and sensors at substrate. In this document, recent progress of process technology for pixel detector is described.

FD-SOI Technology

We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and drain (S/D) structure. The device shows a super steep SS (<;6mV/dec) over 3 decades of the drain current with an ultralow drain voltage down to 0.1V. It also shows a low leakage current (below 1pA/um), a good Id-Vd characteristic and a negligible hysteresis characteristic.

Progress of FD-SOI technology for monolithic pixel detectors

An X-ray irradiation degradation mechanism has been investigated for fully depleted-silicon-on-insulator (FD-SOI) p-channel MOSFETs (p-MOSFETs). It is found that the drain current degradation by the X-ray irradiation has gate length dependence showing 20% degradation for L = 0.2 μm, while 8% for L = 10 μm after the 1.4 kGy(Si) X-ray irradiation. Using Teradas method, it was found that the degradation is not due to mobility degradation but due to radiation-induced gate length modulation (RIGLEM) and the associated increase of source and drain parasitic resistance. The major cause of degradation induced by the RIGLEM is explained by an analytical model, assuming a positive charge generation in sidewall spacers. It can be suggested that the X-ray irradiation degradation of FD-SOI p-MOSFET can be improved by optimizing the lightly doped drain region.

Super steep subthreshold slope PN-body tied SOI FET with ultra low drain voltage down to 0.1V

A high-speed experimental method to evaluate the X-ray radiation damage of a large number of transistors has been developed. In this method, test-element groups (TEGs), including approximately 10,000 metal-oxide-semiconductor (MOS) transistors, were formed on a silicon-on-insulator (SOI) wafer and irradiated with X-rays using novel equipment. After irradiation, fuses on the wafer were cut to isolate each transistor, and the transistor characteristics were measured by an automatic probe station. This method can provide approximately 10,000 lines of I-V curves of the transistors under 31 irradiation dose conditions in 10 days. Radiation damages are known to largely depend on the bias voltage conditions of the devices. In this method, the TEGs are located apart from one another on the wafer; then, the X-ray doses and bias voltage can be controlled specifically by each TEG. Using this equipment, a large amount of experimental data can be effectively acquired. The statistical data analysis enables highly effective radiation-resistant semiconductor development and reliability examination.

Analysis of Effective Gate Length Modulation by X-Ray Irradiation for Fully Depleted SOI p-MOSFETs

We are developing monolithic pixel sensors based on a 0.2 μm fully-depleted silicon-on-Insulator (SOI) technology. The major issue in applications them in high-radiation environments is the total ionization damage (TID) effects. The effects are rather substantial in the SOI devices since the transistors are enclosed in the oxide layers where generated holes are trapped and affect the operation of the near-by transistors. The double SOI sensors that provide an independent electrode underneath the buried oxide layer have been developed. We have irradiated transistor test elements and pixel sensors with γ-rays. By adjusting the potential of this electrode, the TID effects are shown to be compensated. The pixel sensor irradiated to 20 kGy recovered its functionality by applying a bias to the electrode. The radiation tolerance of the SOI devices has been substantially improved by the double SOI.

Development of Experimental Methodology for Highly Efficient Wafer-Level Evaluation of X-Ray Radiation Effects on Semiconductor Devices

Shunsuke HONDA∗A, Kazuhiko HARAA, Kohei TSUCHIDAA, Mari ASANOA, Naoshi TOBITAA, Tatsuya MAEDAA, Yasuo ARAIB, Toshinobu MIYOSHIB, Takeshi TSURUC, Morifumi OHNOD, Noriyuki MIURAE, Hiroki KASAIE, Masao OKIHARAF A University of Tsukuba B High Energy Accelerator Research Organization (KEK) C Kyoto University D National Institute of Advanced Industrial Science and Technology (AIST) E Lapis Semiconductor Miyagi Co., Ltd. F Lapis Semiconductor Co., Ltd. E-mail: honda@hep.px.tsukuba.ac.jp

Total ionization damage effects in double silicon-on-Insulator devices

It was demonstrated that the body bias appearing the super steep Subthreshold Slope (SS) reduces from over 5V to below 1V on the PN-body tied SOIFETs which show the super steep SS with the ultralow drain voltage of 0.1V, when the impurity concentration of the N region on the body tied area is redesigned from the high concentration of the N+ to the low N-. The 3D device simulations also confirmed it and indicated that the optimum length of the N region exits on the different impurity concentration of it for appearing the super steep SS with the low body bias.

Total Ionization Damage Compensations in Double Silicon-on-Insulator Pixel Sensors

The interrelation between off-leakage as consideration of low-power operation and X-ray radiation hardness has been evaluated in view of optimizing the lightly doped drain (LDD) concentration of fully depleted silicon-on-insulator pMOSFET. The MOSFET with relatively low LDD concentration called ultralow-power P channel LDD (ULP-PLDD) shows a lower off-leakage of 0.1 pA/μm but limited X-ray radiation tolerance, such that the drain current is reduced by ~80% after 112-kGy(Si) X-ray irradiation due to radiation-induced gate length modulation (RIGLEM), while the MOSFET with six times higher LDD concentration called radiation-hardened PLDD (RH-PLDD) shows much higher radiation tolerance that the drain current reduction is ~20% for the same radiation dose because of RIGLEM improvement by the elimination of the offset structure employed in ULP-PLDD. The off-leakage of RH-PLDD is one order of magnitude higher than that of ULP-PLDD as <;1 pA/μm. It is shown that there is such a tradeoff between low-power operation and radiation hardness.

Super steep subthreshold slope PN-body tied SOI FET's of ultra low drain voltage=0.1V with body bias below 1.0V

We have fabricated monolithic pixel sensors in 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide, which has many advantages. However, it has been found that the applied electric field in the sensor layer also affects the transistor operation in the adjacent circuit layer. This limits the applicable sensor bias well below the full depletion voltage. To overcome this, we performed a TCAD simulation and added an additional p-well (buried pwell) in the SOI process. Designs and preliminary results are presented.