Masaru Koyanagi
Toshiba
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Publication
Featured researches published by Masaru Koyanagi.
international solid-state circuits conference | 2008
Kazushige Kanda; Masaru Koyanagi; Toshio Yamamura; Koji Hosono; Masahiro Yoshihara; Toru Miwa; Yosuke Kato; Alex Mak; Siu Lung Chan; Frank Tsai; Raul Adrian Cernea; Binh Le; Eiichi Makino; Takashi Taira; Hiroyuki Otake; Norifumi Kajimura; Susumu Fujimura; Yoshiaki Takeuchi; Mikihiko Itoh; Masanobu Shirakawa; Dai Nakamura; Yuya Suzuki; Yuki Okukawa; Masatsugu Kojima; Kazuhide Yoneya; Takamichi Arizono; Toshiki Hisada; Shinji Miyamoto; Mitsuhiro Noguchi; Toshitake Yaegashi
NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.
international solid-state circuits conference | 2012
Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yuui Shimizu; Takahiro Shimizu; Tomohiko Sugimoto; T. Kobayashi; K. Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; Takeshi Ogawa; J. Nakai; Kiyoaki Iwasa; Masatsugu Kojima; T. Suzuki; Yuya Suzuki; S. Sakai; Tomofumi Fujimura; Y. Utsunomiya; Toshifumi Hashimoto; Makoto Miakashi; N. Kobayashi; M. Inagaki; Yoko Matsumoto; Satoshi Inoue; D. He; Y. Honda; Junji Musha
NAND flash memory is widely used in digital cameras, USB devices, cell phones, camcorders and solid-state drives. Continuous lowering of bit cost, increasing flash-memory-die densities and improving performance have helped to expand flash markets. Recently, there are two different directions to meet market demands. One is lowering bit cost and increase memory density to the utmost limit, which is achieved by 4b/cell [1] or 3b/cell [2]. The other is focusing on high performance and high reliability. To meet both demands, we develop a 19nm 112.8mm2 64Gb 2b/cell NAND flash memory with the smallest die size ever reported. 15MB/s programming throughput and 400Mb/s/pin 1.8V Toggle Mode interface [3] are achieved for the first time. Die Micrograph and features are shown in Figure 25.1.1.
IEEE Journal of Solid-state Circuits | 1990
J.-I. Okamura; Y. Okada; Masaru Koyanagi; Yoshiaki Takeuchi; M. Yamada; Kiyofumi Sakurai; S. Imada; S. Saito
The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a V/sub cc/ of 4 V at 85 degrees C. >
Archive | 2001
Manami Kudou; Masaru Koyanagi
Archive | 1992
Masaru Koyanagi; Minoru Yamda
Archive | 1995
Yoshiaki Takeuchi; Hiroaki Tanaka; Masaru Koyanagi
Archive | 1992
Ryosuke Matsuo; Masaru Koyanagi
Archive | 1991
Hiroaki Tanaka; Masaru Koyanagi
Archive | 2002
Masaru Koyanagi; Kaoru Nakagawa; Takahiko Hara; Satoru Takase
Archive | 2006
Tohru Kimura; Masahiro Yoshihara; Masaru Koyanagi