Kazuyoshi Muraoka

An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application

A multiple-level 2-bit/cell storage technique for DRAMs (dynamic random-access memories) has been developed. The total RAM area is reduced and the cell array is cut in half. Since the memory cell area is especially defect-sensitive, this technique is highly effective for process yield improvement. Reasonable access time has been realized with this technique: 170 ns is still fast enough for many ASIC (application-specific integrated circuit) memory applications. This technique meets the requirement of high density and moderate speed. It was found that the 2-bit/cell storage technique is suitable for macrocell or memory-on-logic type application. >

7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology

The demand for high-throughput NAND Flash memory systems for mobile applications such as smart phones, tablets, and laptop PCs with solid-state drives (SSDs) has been growing recently. To obtain higher throughput, systems employ multiple NAND Flash memories operating simultaneously in parallel. The available power for a mobile device is severely restricted and the peak total operating current may be high enough to cause large supply-voltage drop or even an unexpected system shutdown. Therefore it is important for NAND Flash memories to reduce operating power and peak operating current.

A high random-access-data-rate 4 Mb DRAM with pipeline operation

A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e. a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAD access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family

A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs

A latch-up-like failure phenomenon that shows hysteresis in the V/sub cc/-I/sub cc/ characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is discussed. This failure is caused by large substrate-current generation due to the depletion-mode threshold voltage of n-channel transistors at near-zero substrate-bias operation. It is increasingly important not only to design a powerful substrate-bias generator but also to suppress the back-gate bias effect on the n-channel transistor. >

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology

A 75 mm2 low power 64 Gb MLC NAND flash memory capable of 30 MB/s program throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm CMOS technology. 36% power reduction from 3.3 V design is achieved by a new pumping scheme. New low current peak features reduce a multi-die concurrent programming peak by 65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors reducing bit-line discharge time by 70% is introduced to improve performance.

A 12 MHz data cycle 4 Mb DRAM with pipeline operation

A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 mu m twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random access storage (RAS) input cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the inverted RAS input cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95 ns inverted RAS input cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAMs. >