Masashi Horiguchi

Review and future prospects of low-voltage RAM circuits

This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of low-voltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, VT, and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

Low-voltage limitations of memory-rich nano-scale CMOS LSIs

The low-voltage limitations of memory-rich nano-scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip-flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger VT variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI as well as by using repair techniques. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: high-VDD bulk CMOS LSIs for low-cost low-standby-current applications and low-VDD FD-SOI LSIs for low-power applications.

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

The authors present two developments for DRAM voltage limiters: a precise internal-voltage generator composed of a PMOS threshold-voltage-difference generator and a tunable voltage-up converter with fuse trimming; and a stabilized driver composed of a feedback amplifier with compensation for a time-dependent load. These circuits provide a voltage not susceptible to the supply-voltage and substrate-voltage bouncings, temperature variation, and threshold-voltage deviation due to the process fluctuation, while maintaining CMOS-DRAM process compatibility. Moreover, feedback-loop stability and frequency response are maintained by ensuring a phase margin of 55d at a unity-gain frequency of 10 MHz using compensation through zero insertion. Implementation of these new circuits in a 16-Mb CMOS DRAM is reported

A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from −50°C to +150°C using piecewise-linear-current curvature compensation

A sub-1V 3.9μW bandgap reference (BGR) with small voltage variation of ±0.34% and low temperature drift (1mV) over a wide temperature range (-50°C ~ +150°C) and a wide voltage range (+0.9 V ~ +5.5V) by using a low power current mode BGR core and a piecewise-linear curvature compensation system. The BGR occupies 0.1mm² in 0.13μm CMOS technology with triple well structure.

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs

The feasibility of 0.5-V memory-rich nanoscale CMOS LSIs was studied. First, repair techniques and nanoscale FD-SOI MOSTs are discussed in terms of Vt-variation. Second, sub-0.5-V dual-VDD dual-Vt logic circuits are proposed and evaluated by simulation with a 25-nm planar FD-SOI MOST, followed by an investigation of a 0.5-V 1-Gb SRAM/DRAM. Third, the importance of using compensation circuits for process, voltage, and temperature variations is stressed. Finally, it is concluded that a 0.5-V memory-rich CMOS LSI is possible while reducing the power to one-tenth that of a conventional 1-V CMOS LSI if the above devices and circuits are used and the within-wafer Vt-variation is compensated for.