Masato Koutani

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor

A fully integrated direct conversion DVB-H tuner is realized in a 0.5-mum SiGe BiCMOS technology. To meet the stringent linearity requirement while keeping low power consumption, novel linearization techniques for a variable-gain low-noise amplifier (VG-LNA) and a mixer are proposed. The proposed linearized VG-LNA has a variable gain range of over 50 dB, noise figure of less than 2.6 dB over the frequency range from 200 to 1000 MHz, and IIP3 of more than -10 dBm at a current consumption of 2.1 mA. The quadrature mixer with the proposed linearization technique achieves OIP3 of more than 25 dBm at a current consumption of 5 mA. In addition, a new offset-cancel feedback is introduced for the baseband block of a direct conversion receiver, which keeps the high-pass cutoff frequency independent of the baseband VGA gain. The fabricated tuner IC satisfies all the DVB-H requirements at a power consumption of 184 mW

A digital terrestrial television (ISDB-T) tuner for mobile applications

A 160mW low-IF single-chip tuner for a mobile ISDB-T receiver is realized in SiGe BiCMOS. Its 25mW variable gain LNA shows 2.7dB NF and 62dB variable gain range. The 20mW switched-capacitor channel selection filter exhibits 80dB out-of-band rejection and 11nV//spl radic/Hz input referred noise.

A 184mW Fully Integrated DVB-H Tuner Chip with Distortion Compensated Variable Gain LNA

A single chip direct conversion DVB-H tuner with a distortion compensated variable gain LNA is implemented in 0.5mum SiGe BiCMOS. The LNA exhibits 0dBm IIP3 and 2.8dB NF at 860MHz. A new offset cancel feedback is introduced that keeps the cutoff frequency independent of the baseband gain. The IC consumes 184mW at 2.8V while achieving a sensitivity of -96dBm for QPSK, CR=1/2 signal

A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications

An ISDB-T 1-segment RF and BB chipset with adaptive bias-current control is presented. The BB IC monitors MER and dynamically sets the bias current of RF sub-circuits. In the worst reception case, the chipset consumes 105mW. In the absence of strong interferences, the adaptive control reduces the consumption down to 77mW without performance degradation.

A highly linear CMOS buffer circuit with an adjustable output impedance

An output buffer circuit with an adjustable output impedance and high linearity is presented. The buffer circuit employs two kinds of feedback strategies, which enable it to drive a low impedance load without power increase. A differential buffer circuit with 20-ohm output impedance has been fabricated in a 0.25-/spl mu/m CMOS process. The measured IIP3 is over 30 dBm for frequencies up to 100 MHz and the power consumption is 93.1 mW with a 3.3-V power supply.

A high OIP3 quadrature mixer using cross-coupled transconductor

A new quadrature mixer topology, utilizing cross-coupled transconductance stages for linearity improvement is presented. The fabricated mixer showed OIP3 of 129.6 dBmuV (resp. 133.8 dBmuV), input referred noise of 4.7 nV/radicHz (resp. 5 nV/radicHz) with current consumption of 3.8 mA (resp. 4.8 mA) at a 2.9-V supply voltage using a 0.5-mum BiCMOS process

RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers

RF Variable Gain Amplifiers (RF-VGA) are important components for integrated TV broadcast receivers. Analog and digital controlled RF-VGAs are compared in terms of linearity and an AGC loop architecture suitable for digitally controlled RF-VGA is proposed. Further linearity enhancement applicable for CMOS implementation is also discussed.