Shuichi Kawama

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor

A fully integrated direct conversion DVB-H tuner is realized in a 0.5-mum SiGe BiCMOS technology. To meet the stringent linearity requirement while keeping low power consumption, novel linearization techniques for a variable-gain low-noise amplifier (VG-LNA) and a mixer are proposed. The proposed linearized VG-LNA has a variable gain range of over 50 dB, noise figure of less than 2.6 dB over the frequency range from 200 to 1000 MHz, and IIP3 of more than -10 dBm at a current consumption of 2.1 mA. The quadrature mixer with the proposed linearization technique achieves OIP3 of more than 25 dBm at a current consumption of 5 mA. In addition, a new offset-cancel feedback is introduced for the baseband block of a direct conversion receiver, which keeps the high-pass cutoff frequency independent of the baseband VGA gain. The fabricated tuner IC satisfies all the DVB-H requirements at a power consumption of 184 mW

A digital terrestrial television (ISDB-T) tuner for mobile applications

A 160mW low-IF single-chip tuner for a mobile ISDB-T receiver is realized in SiGe BiCMOS. Its 25mW variable gain LNA shows 2.7dB NF and 62dB variable gain range. The 20mW switched-capacitor channel selection filter exhibits 80dB out-of-band rejection and 11nV//spl radic/Hz input referred noise.

A 23 mW 256-tap 8 MSample/s QPSK matched filter for DS-CDMA cellular telephony using recycling integrator correlators

In direct sequence code division multiple access (DS-CDMA), matched filters calculate the cross-correlation function of a received signal spread by a pseudo-random noise (PN) sequence and a replica PN sequence. A matched filter like this can be viewed as a finite impulse response (FIR) filter with a PN sequence used as the binary tap weights, minimizing search and synchronization times in DS-CDMA receivers. This paper introduces an approach for implementing matched filters based on recycling integrator correlators (RICs) that use a sensible combination of analog and digital processing to minimize area and power consumption. The matched filter is organized by combining an array of RICs, a cyclic shift register which stores a PN sequence, and a rotary multiplexer which transfers the correlation values one by one. This implementation provides: 1) an input analog signal processing capability without the need of a fast ADC; 2) an already digitally-coded output stream; 3) small capacitor ratios for the switched-capacitor (SC) integrators; and 4) minimum die-area and current consumption for the available technology and the spreading ratio, that is, the length of the PN sequence. The fabrication process is a 0.35 /spl mu/m CMOS double-metal, double-poly process. The chip occupies 22.8 mm/sup 2/ and dissipates 23 mW with a 1.8 V power supply.

Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation

A combination of continuous-time and switched capacitor integrators in a simulated LC lossless ladder yields a response with suppressed aliasing without the use of continuous-time prefiltering. Fabricated in a 0.35-/spl mu/m CMOS process, a fifth-order Cauer low-pass filter for a W-CDMA cellular phone receiver has a cutoff frequency of 1.92 MHz and aliasing suppression of better than 40 dB for 30.72-MHz sampling. Without using any tuning mechanism, a 10% accuracy of the cutoff frequency is achieved. As additional features, the filter has variable gain from -13.3 to 16.4 dB and an offset compensation mechanism. With the latter, a 50-mV dc offset added to the input is suppressed to 11 mV or less at the filter output under the maximum gain setting. The filter consumes 2.81 mA at 1.8-V power supply in a die area of 0.62 mm/sup 2/.

A 184mW Fully Integrated DVB-H Tuner Chip with Distortion Compensated Variable Gain LNA

A single chip direct conversion DVB-H tuner with a distortion compensated variable gain LNA is implemented in 0.5mum SiGe BiCMOS. The LNA exhibits 0dBm IIP3 and 2.8dB NF at 860MHz. A new offset cancel feedback is introduced that keeps the cutoff frequency independent of the baseband gain. The IC consumes 184mW at 2.8V while achieving a sensitivity of -96dBm for QPSK, CR=1/2 signal

A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications

An ISDB-T 1-segment RF and BB chipset with adaptive bias-current control is presented. The BB IC monitors MER and dynamically sets the bias current of RF sub-circuits. In the worst reception case, the chipset consumes 105mW. In the absence of strong interferences, the adaptive control reduces the consumption down to 77mW without performance degradation.

CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops

The recycling integrator correlator (RIC) is a novel approach for implementing correlators that consumes less power than conventional digital or analog CMOS correlators. The RIC modulates the product of a received signal and a pseudorandom noise (PN) sequence into a bit stream by first-order /spl Delta//spl Sigma/ modulation. The accumulated number represents the quantized correlation value. Using RICs, two functional blocks of a direct sequence code division multiple access (DS-CDMA) demodulator targeting IMT-2000, a matched filter (MF) and a delay locked-loop (DLL) are implemented in silicon. In the fabricated 256-tap QPSK MF-RIC, two 256-tap double-sampling MFs sample the I and Q received analog signals at a rate of 8 Msample/s. Their outputs are 9-bit quantized correlation values with a 256-chip PN sequence at the same rate as the sampling rate. The DLL-RIC can adapt to spreading ratios from 32 to 256 with the use of an auxiliary ADC that can compensate the degradation of dynamic range when the spreading ratio is small. Processed in a 0.35-/spl mu/m CMOS process, the MF-RIC and the DLL-RIC, respectively, occupy 22.8 and 2.28 mm/sup 2/ and dissipate 23.0 and 3.4 mW at 2-V power supply.

Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay Calibration

An automatic tuning method for active-RC base-band filters used in direct conversion receivers is proposed. Filter calibration is realized by setting the phase delay for a reference frequency of 4.5 MHz to -360deg. The proposed method is accurate and area efficient, since it does not require a replica filter but uses the filter itself. In addition, monotonic control of the capacitor arrays makes fast tuning possible. A pair of base band filters for DVB-H receivers including this automatic tuning method was fabricated using a 0.5mum SiGe Bi-CMOS process. The accuracy of the tuning is limited by the resolution of the binary capacitor-array and is 12deg. This corresponds to a worst case cutoff frequency deviation of 300 kHz. The tuning takes 113.8musec

A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator

A Delay Locked-Loop (DLL) for a 5-Mcps DS-CDMA demodulator targeting IMT-2000 has been implemented consisting of six correlators, each one incorporating a form of /spl Delta//spl Sigma/ modulation called recycling integrator to obtain a quantized correlation value between a received signal and PN sequence. The DLL can adapt to spreading ratios from 32 to 256 with an auxiliary ADC complementing the dynamic range degradation when the ratio is small. Fabricated in 0.35-/spl mu/m double-metal double-poly CMOS process, the chip occupies 2.28 mm/sup 2/ and dissipates 3.7 mW with a supply voltage of 2 V.

Embedded anti-aliasing in switched-capacitor ladder filters

A combination of continuous-time and switched-capacitor integrators in a simulated LC loss-less ladder yields a response with suppressed aliasing without using continuous-time pre-filtering. Fabricated in a 0.35-/spl mu/m CMOS process, a fifth-order Cauer low-pass filter has a cutoff frequency of 1.92 MHz and aliasing suppression of better than 40 dB. Without using any tuning mechanism, /spl plusmn/10% accuracy of the cut-off frequency is achieved. It consumes 3.7 mA at 1.8-V power supply in a die-area of 0.27 mm/sup 2/.