Masatoshi Morikawa

High power LDMOS for cellular base station applications

A 2.2-GHz Si Power LDMOS (Laterally Diffused MOS) with an output power of 150 W and a drain efficiency of 47%, both higher than that of conventional devices, was developed for cellular base station applications. Also higher reliability is ensured by preventing the hot electron degradation. The LDMOS has a double-doped offset structure and an SG (Second Gate) structure.

A 30-V, 75-m/spl Omega/*mm/sup 2/ power MOSFET for intelligent driver LSIs

An extremely low on-resistance Lateral DSA MOSFET(LDM0S) is developed for intelligent driver LSIs. This device has an improved meshed gate structure with double-layer A1 electrodes. Drain offset layer doping is introduced to decrease drain series resistance, and an A1 field plate is formed by the first A1 layer to reduce electric field at the substrate surface. A 30-V breakdown voltage and a 75-m!2=mm2 onresistance are obtained in the device fabricated by a 1.5pm BiCMOS process. The on-resistance is reduced 20% compared with conventional devices. An H-bridge driver is designed using those devices, and a very lowpower dissipation is achieved.

High-efficiency Complementary Power Mos Pwm Driver Lsi With Low-loss Full-mode Sensing

A high-efficiency complementary power MOS LSI technology is developed for PWM motor drivers. A top-side PWM method with about 1% loss and fullmode detectable current sense, and low on-resistance power MOSFETs with shield structures are newly introduced.