Takeaki Okabe

Thermal stability and secondary breakdown in planar power MOSFET's

The destructive secondary-breakdown mechanism of high-voltage n-channel power MOSFETs is discussed. A model is proposed in which the secondary breakdown is caused primarily by the negative-resistance effects of a parasitic bipolar transistor structure. The model suggests that destructive breakdown can be suppressed by a new no-surface-breakdown structure fabricated on a p-on p+epitaxial wafer. Power MOSFETs having this structure have been realized and are completely free from secondary breakdowns, as suggested by the model. In addition, experimental evidence for excellent thermal stability of the power MOSFET is given by infrared scanner measurements of the temperature rise in the chip compared with bipolar transistors. An n-channel planar power MOSFET with a 400-W power limitation at 220-V breakdown voltage and a maximum current of 12 A has been successfully fabricated.

Extremely high efficient UHF power MOSFET for handy transmitter

A UHF Power MOSFET suitable for use in handy transmitter is reported, which can deliver 5.0W of output power with 72% drain efficiency and 6.0dB gain at 860MHz for 7.5V low supply voltage. A new Power MOSFET is analyzed by two dimensional computer simulation to realize low voltage operation at ultra high frequency. This device has a Bi-Well Structure for low on resistance and small parastic capacitance. For high frequency performance, 1.3µm channel length and metal gate are empolyed. This device has also very wide band frequency characteristics and is able to withstand infinite VSWR. Thus, a UHF Power MOSFET is considered to be a significant candidate for handy telephone, mobile radio and other handy communication systems.

A complementary pair of planar-power MOSFET's

A complementary pair of planar-power MOSFETs has been developed, each of which has drain breakdown voltage as high as 250 V and 12-A current capability. These devices have field plates on the ion-implanted gate offset region to realize high-breakdown voltages and large current capabilities. The field distribution behavior of a field-plated high-voltage MOSFET and a non-field-plated device are compared. In this procedure, the first-order theory of pinchoff voltage of the offset region, the most important parameter for a planar-power MOSFET, is derived for high-voltage and high-current capability design. Experimental results to support the usefulness of a field plate for improving breakdown voltage and current capabilities are obtained and discussed. Finally, future possible developments of these devices, such as high-voltage and high-current approaches, are described and a new type of device structure is proposed.

An advanced bipolar-MOS-I 2 L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I2L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (\leq 2 \microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n+buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.

A complementary-pair of high-power MOSFET's

A complementary pair of high power MOSFETs is developed, each of which has a drain breakdown voltage as high as 200V and 10A current capabilities. This device has an offset gate and an ion-implanted additional channel to realize this high breakdown voltage. The device structure including the use of a field plate, is optimized by two dimensional MOS analysis. This design and a highly refined polysilicon gate fabrication process contribute to the realization of the high power devices. Measurement of these devices reveals superior thermal characteristic and assures a larger ASO than that of conventional bipolar transistors of the same chip size.

AC-bias annealing effects on radiation-induced interface traps (MOS transistors)

High-frequency AC-bias annealing effects on interface traps are extensively discussed and explained using a model with AC-bias-activated carriers. AC-bias annealing causes a reduction in the broad peak above the midgap in the energy distribution of interface traps. The phenomenon is independent of gate electrode materials in MOS transistors. There is an offset voltage window for decreasing interface-trap density. The frequent transition between accumulation and inversion is responsible for AC-bias annealing effects. A model is proposed in which the AC-bias-activated electrons recombine with holes and the resultant excess energy changes the defect silic.on state into another state. The proposed model is supported by a recombination enhanced defect reaction process and verified by analyzing the temperature dependence of the AC-bias annealing. >

Radiation effects on ion-implanted silicon-dioxide films

The effects of radiation on SiO/sub 2/ films implanted with high ion doses are studied. The interface-state buildup is suppressed by the ion-implanted oxide. The amount of suppression depends on the ion dose, the gate bias during irradiation, and the annealing atmosphere. A radiation-hardening technique for field oxide is proposed, using the ion-implanted oxide. Radiation-induced interface-state density is suppressed by one order of magnitude using arsenic implantation. By applying this technique to a conventional bipolar process, current gain reduction is suppressed to within 10% after 10/sup 6/ rad(SiO/sub 2/) irradiation. >

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.

Computer analysis of breakdown mechanism in planar power MOSFET's

Breakdown mechanism in planar power MOSFETs having high breakdown voltage is investigated. Precise electric field distribution is obtained by two-dimensional numerical analysis. This field distribution is used to optimize device structure and to predict breakdown voltage. A technique for reducing the electric field on the silicon surface by equalizing its distribution is presented.

Radiation effects on UHF power MOSFETs

The effects of ionizing radiation of UHF power MOSFETs are studied. It is found that a power MOSFET amplifier exhibits little change in output power and efficiency in the linear region, but it is seriously degraded in the saturation region. The reason for this degradation is an increase in on-resistance and a decrease in the maximum current, both caused by radiation-induced interface states. A MOSFET exposed to radiation while it is operating as an amplifier at 860 MHz has a different threshold voltage shift than one not operating at high-frequency. This phenomenon can be explained by the annealing effect of the high-frequency electric field across the gate. For improvement in radiation tolerance, a device with a thinner thermal oxide film on the offset region is proposed and discussed. >