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Dive into the research topics where Masatoshi Yasunaga is active.

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Featured researches published by Masatoshi Yasunaga.


IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A | 1995

Chip scale package: "a lightly dressed LSI chip"

Masatoshi Yasunaga; Shinji Baba; Mitsuyasu Matsuo; Hironori Matsushima; Shin Nakao; Tom Tachikawa

A new flip-chip-like package named chip scale package (CSP) has been developed. It is constructed of LSI chips, thin resin coats, and electrode balls, having no leadframe nor any bonding wires. Wiring conductor patterns were used for electrical connection between internal pads on the die and external electrode balls. Also the transfer-bumping technique was applied for inner bump formation. Finally, solder joint life when mounted onto typical boards was estimated by simulation. >


IEEE Transactions on Components, Hybrids, and Manufacturing Technology | 1990

New developed of thin plastic package with high terminal counts

Masanobu Kohara; Shin Nakao; Masatoshi Yasunaga; Yoshihiko Nemoto; Osamu Nakagawa; Haruo Shimamoto; Yasutsugu Tsutsumi

A small and thin quad flat package (QFP)-type plastic package for large-scale integrated (LSI) logic devices with high pin counts has been developed. The size of the package with 252 input and output pins is 17.3 mm by 17.3 mm, and the thickness is 1.52 mm. The pitch and the width of the leads are 0.25 and 0.1 mm, respectively. The main technologies for assembly of the package are tape automated bonding (TAB) interconnection technology, which has been developed for bonding of high-terminal-count LSIs, and the molding technology, which has also been developed for very small and thin plastic packages. The reliability of the package and the outer lead bonding of the package were evaluated, and it was confirmed that both the package and the bonding have no problem in the pressure cooker test (PCT), the temperature cycle test, and the high-temperature-storage test. >


electronic components and technology conference | 2002

New thermal fatigue life prediction method for BGA/FBGA solder joints with basic crack propagation study

Yasumi Uegai; Akinobu Kawazu; Qiang Wu; Hironori Matsushima; Masatoshi Yasunaga; Haruo Shimamoto

Evaluation of the thermal fatigue life of the solder joints that connect the BGA package to the system board electrically and mechanically, and the improvement of precision are important issues in the development of BGA/FBGA packages. The fatigue life of the BGA solder joint consists of a process of micro-crack initiation followed by its propagation. This results in the increase of electrical resistance and the lifetime of solder joint. It is necessary to develop an evaluation method using crack growth - which defines most of the total life - for more accurate prediction of the lifetime of BGA/FBGA solder joints. The fatigue crack growth rate of BGA solder joints was measured by using actual BGA solder joint specimens in order to evaluate the thermal cycle life of BGA packages. Eutectic solder was used for the solder joint material. Isothermal mechanical fatigue tests were performed on these specimens and thermal cycle tests were performed under the temperature condition of 0/spl lrarr2/+100/spl deg/C. The crack propagation length was measured by observing the fracture surface of the solder joint before the joint was broken interrupting the fatigue test. The fatigue crack growth rate was then evaluated. A structural analysis using FEM was made to determine the equivalent plastic strain and the plastic strain energy density of BGA solder joints in consideration of the nonlinear stress-strain relation of the solder material. The fatigue crack growth curve of BGA solder joints was evaluated combining the above experimental and analytical results.


Archive | 2014

Lead frame and semiconductor device

Masatoshi Yasunaga; Masanobu Kohara


Archive | 1991

Method of fabricating semiconductor device having sidewall spacers and oblique implantation

Masahiro Shimizu; Katsuyoshi Mitsui; Yomiyuki Yama; Masatoshi Yasunaga


Archive | 1994

Resin seal semiconductor package

Masatoshi Yasunaga; Shin Nakao; Shinji Baba; Mitsuyasu Matsuo; Hironori Matsushima


Archive | 1999

Resin seal semiconductor package and manufacturing method of the same

Masatoshi Yasunaga; Shin Nakao; Shinji Baba; Mitsuyasu Matsuo; Hironori Matsushima


Archive | 1993

Resin-sealed semiconductor package and fabrication thereof

Shinji Baba; Mitsuyasu Matsuo; Hirotsugu Matsushima; Shin Nakao; Masatoshi Yasunaga; 伸 中尾; 雅敏 安永; 光恭 松尾; 弘倫 松嶋; 伸治 馬場


Archive | 2000

Method of manufacturing a packaged semiconductor device, and a semiconductor device manufactured thereby

Masatoshi Yasunaga; Michitaka Kimura; Satoshi Yamada


Archive | 1991

METHOD FOR MANUFACTURING A RESIN ENCAPSULATED SEMICONDUCTOR DEVICE

Masatoshi Yasunaga; Masanobu Kohara

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